• State Accepted Answer
  • Locked Locked
  • Replies 3 replies
  • Subscribers 349 subscribers
  • Views 4899 views
  • Users 0 members are here
2025 survey

We are running a survey to help us improve the experience for all of our members. If you see the survey appear, please take the time to tell us about your experience if you can.

Options
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Question regarding A15 L2ACTLR register programming (auto clock gating)

Thomas P Abraham

Hi,

This question is regarding Cortex-A15 L2ACTLR[27] bit ("Force L2 logic clock enable active"). If the clock to L2 block has to be forced to be active all the time (L2ACTLR[27] = 1), is it sufficient if one of the A15 Cores in the MPCore setting this bit? Or does all the four CPUs in the A15 MPcore need to set this bit?

Thanks,

Thomas.

Parents
  • 0 in reply to chinatiger

    Hi Chinatiger,

    Thanks for talking a look. But the question was more about how many A15 CPUs in a Quad A15 MPCore should set the ACTLR[27] bit?

    Is it correct to say that, if any one of the A15 CPU in a Quad A15 MPCore sets ACTLR[27] bit is sufficient to disable the L2 auto clock gating feature?

    Thanks,

    Thomas.

Reply
  • 0 in reply to chinatiger

    Hi Chinatiger,

    Thanks for talking a look. But the question was more about how many A15 CPUs in a Quad A15 MPCore should set the ACTLR[27] bit?

    Is it correct to say that, if any one of the A15 CPU in a Quad A15 MPCore sets ACTLR[27] bit is sufficient to disable the L2 auto clock gating feature?

    Thanks,

    Thomas.

Children