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Instruction availability

Jens Bauer

I've seen code using both positive and negative right-shifted register indexing.

These instructions do not seem to be available on Cortex-M or Cortex-A (thumb-mode).

I've seen them available for ARM7TDMI (in 32-bit ARM mode)

Example:

  •      str     r0,[r1,r2,asr#5]      /* positive right-shifted register offset */
  •      str     r0,[r1,-r2,lsl#2]     /* negative shifted register offset */
  •      str     r0,[r1,-r2,asr#5]     /* negative right-shifted register offset */
  •      str     r0,[r1,-r2,asr#12]!   /* negative right-shifted register offset with update */

What's the most recent (or fastest) ARM processor family that implement these instructions ?

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