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I've seen code using both positive and negative right-shifted register indexing.
These instructions do not seem to be available on Cortex-M or Cortex-A (thumb-mode).
I've seen them available for ARM7TDMI (in 32-bit ARM mode)
Example:
What's the most recent (or fastest) ARM processor family that implement these instructions ?
Looking at the register offset page in the ARM help, Table 4.3 seems to imply that right shifted register offset (ASR) should be available on all architectures in ARM mode word and byte instructions. Thumb node only has left shifted offset (LSL) according to the same table.
Thank you very much for your quick reply.
In fact, I expected that. Would the latest architecture that supports "ARM mode" be the ARM11; eg. the latest non "thumb-only" ?
There are some instruction-features that I'd really like to get from the 'full' 32-bit ARM instruction set.