What is Early write acknowledgement?

Thanks very much. That is different from what I was thinking of which I think was an old facility to try and achieve something similar.

I assume what happens with this then is that once the data is buffered the system assumes it can be written okay the same as data from the cache can always be written back to memory.

Thanks very much. That is different from what I was thinking of which I think was an old facility to try and achieve something similar.

I assume what happens with this then is that once the data is buffered the system assumes it can be written okay the same as data from the cache can always be written back to memory.

My feeling is that they help different use cases.

Early write response helps by giving a response on the first beat of a burst, this is great if your endpoint is a memory controller with it's address space mapped as Normal, i.e. you can be very bursty since you can gather and reorder, you can essentially treat every write as having a single beat throughput and take advantage of big buffers.

Early write acknowledge helps by allowing a transaction - which on Device memory is probably not going to be a burst - to seem complete at some other place than the true endpoint. As interconnects get bigger and more complex, this is obviously important..

A typical use case for early write response is from the dynamic memory controller (DMC). Once a write has entered the buffer or queue in that memory controller it can give an early write response to the system, and write that data to DRAM some time later. One important feature of the memory controller is hazard checking of this write data, for example if there is a write followed by a read, then the read must see the latest data, either directly from the DMC buffer, or DMC could force the write to complete to DRAM before processing the read.

The system architect needs to carefully think about how early write response could be supported elsewhere in the system and ensure there is appropriate hazard checking to ensure correct ordering of data.

I'm less familiar with the early write acknowledgement but I expect there may be similar system level hazards or ordering to consider.

Neil.

Hi Neil,

Consider the peripherals like UART. If I am trying to write the data into TX FIFO of UART whether I can make use advantage of it ?

In case of external memory controller, did you mean it like a feedback mechanism to indicate the successful write transfer ?