Hi all,
What is early write acknowledgement and how this attribute affects the continuous read/write performed on the peripheral/physical memory ?
A typical use case for early write response is from the dynamic memory controller (DMC). Once a write has entered the buffer or queue in that memory controller it can give an early write response to the system, and write that data to DRAM some time later. One important feature of the memory controller is hazard checking of this write data, for example if there is a write followed by a read, then the read must see the latest data, either directly from the DMC buffer, or DMC could force the write to complete to DRAM before processing the read.
The system architect needs to carefully think about how early write response could be supported elsewhere in the system and ensure there is appropriate hazard checking to ensure correct ordering of data.
I'm less familiar with the early write acknowledgement but I expect there may be similar system level hazards or ordering to consider.
Neil.
Hi Neil,
Consider the peripherals like UART. If I am trying to write the data into TX FIFO of UART whether I can make use advantage of it ?
In case of external memory controller, did you mean it like a feedback mechanism to indicate the successful write transfer ?