Good day all,
I'm working with a SOC with dual Cortex-R4 that comes with MPU.
Due to the SRAM limitation and other restrictions, I'm not using any embedded linux or any other SMP RTOS.
Currently I'm working on the optimization of the flow, so I'm trying to study the caches and other MPU options,
in order to gain maximum performance.
Each core has a ATCM and BTCM memory and additional access to shared BTCM memory.
The ATCM/BTCM memories are also accessible via AXI bus , but this adds additional penalty.
The SOC also is connected to external SDRAM which is accessible via AXI bus only.
Currently I'm trying to perform some performance measurements in order to understand the optimal way, how the code should be
placed and accessed by the dual core configuration.
I do see that enabling of the L1 cache for SDRAM AXI port with write through ,no write allocate, shareable attributes, gets me no
cache hits/cache misses (I'm using the PMU to track them). As soon as I remove "shareable" attribute ONLY from MPU region configuration,
I do see a serious boost in performance also the cache starts working (lots of hits/misses).
From my understanding the "shareable" attribute allows to sync the access between different AXI bus slaves to the target (shareable) memory.
So I'm confused, as I've expected to get a penalty due to this sync, but instead it looks like "shareable" attribute somehow disables the L1 cache option at all...
Could someone please explain where my understanding is wrong?
I hope the explanation is not confusing
Regards,
Ilan