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Precise/Imprecise data abort in arm processor

Rakesh Reddy

Hi all

i am new ARM processor. Can anyone explain clearly in simple terms what is Precise/Imprecise data abort in arm processor.?

Parents
  • 0 in reply to Chris Shore

    We are facing Data abort - Asynchronous External abort type. Our understanding about Asynchronous External abort, The exception is not generated as a result of direct execution or attempted execution of instruction that caused the exception.

     Following register dump are collected during Exception handling:

     

    1. spsr_abt           : 0x6000001f
    2. DFSR               : 0x1406
    3. ADFSR             : 0x0
    4. AIFSR              : 0x0
    5. DFAR               : 0x4d033787
    6. sp_abt              : 0x43efdde8
    7. lr_abt                : 0x4000c1c0
    8. sp_sys              : 0x43ef3778
    9. lr_sys               : 0x4010ded0

     DFSR contains -  0x1406

     Exception type bit[12]    : External abort type

    Fault status bit[10, 3:0]   : 0b10110 - Asynchronous external abort

     Over Asynchronous exception DFAR become UNKNOWN. So We expected AxFSR should help in this case. Unfortunately, In all the reproduction AxFSR shows ‘0’.

     And Linker(lr) and Stack Pointer (sp) also points to be (very usual flow) normal SW execution.

    Problem observed in R7 CPU.

      Could you please provide technical advice to identify the source of exception.

     

    • Firstly, Is there any defined method to capture the source of Asynchronous External abort.
    • In specific to RCAR SOC, What are all the possible ways could lead to Asynchronous External abort.
    • Does masking Asynchronous exceptions makes any other invisible side effect.
    • Is it possible that wrong system behaviour in CA5x CPU’s would cross effect or mislead CR7 CPU to Asynchronous External abort.
    • Does this could be related to something wrong with cache operation.
Reply
  • 0 in reply to Chris Shore

    We are facing Data abort - Asynchronous External abort type. Our understanding about Asynchronous External abort, The exception is not generated as a result of direct execution or attempted execution of instruction that caused the exception.

     Following register dump are collected during Exception handling:

     

    1. spsr_abt           : 0x6000001f
    2. DFSR               : 0x1406
    3. ADFSR             : 0x0
    4. AIFSR              : 0x0
    5. DFAR               : 0x4d033787
    6. sp_abt              : 0x43efdde8
    7. lr_abt                : 0x4000c1c0
    8. sp_sys              : 0x43ef3778
    9. lr_sys               : 0x4010ded0

     DFSR contains -  0x1406

     Exception type bit[12]    : External abort type

    Fault status bit[10, 3:0]   : 0b10110 - Asynchronous external abort

     Over Asynchronous exception DFAR become UNKNOWN. So We expected AxFSR should help in this case. Unfortunately, In all the reproduction AxFSR shows ‘0’.

     And Linker(lr) and Stack Pointer (sp) also points to be (very usual flow) normal SW execution.

    Problem observed in R7 CPU.

      Could you please provide technical advice to identify the source of exception.

     

    • Firstly, Is there any defined method to capture the source of Asynchronous External abort.
    • In specific to RCAR SOC, What are all the possible ways could lead to Asynchronous External abort.
    • Does masking Asynchronous exceptions makes any other invisible side effect.
    • Is it possible that wrong system behaviour in CA5x CPU’s would cross effect or mislead CR7 CPU to Asynchronous External abort.
    • Does this could be related to something wrong with cache operation.
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