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The exact definition of outer and inner in ARMv7


I'm reading ARMv7 architecture reference manual and there are the following keywords:

  • outer cacheable
  • inner cacheable
  • outer sharable
  • inner sharable

It looks like that outer/inner cacheable means that a region of memory can be cached in L1 (inner) or L2 (outer).

What I don't understand is the sharability.

According to the manual, it says inner is sharable inside a cluster and outer is sharable among clusters.

Here, what does cluster mean? It looks like a group of cores, but I'm failed to find exact reference about these.

Any help would be appreciated.

  • Hi jaeyong,

    > I'm failed to find exact reference about these.

    There isn't an exact definition of what is in the outer shareable domain. It depends on how the system was built. Basically Inner and Outer shareability define three sets of devices which have a coherent view of memory:

    1. Those inside the inner shareabiltiy domain
    2. Those inside both the inner and outer shareability domain
    3. Those outside both shareability domains

    Data marked as "inner shareable" is only guaranteed to be visible to (1), data marked as "outer shareable" is only guaranteed to be visible to (1) and (2). Anything else (making inner shareable data visible to an outer shareable master, or making any data visible to a device in set (3)) will require manual cache maintenance. One silicon chipset may have many distinct inner and outer shareable domains - e.g. if a chip had two different Cortex-R4 processors implemented then they would each have inner coherency with respect to the themselves.

    The AMBA 4 Coherency Extensions (ACE) extend the notion of outer shareability onto the bus itself, allowing different bus masters to be kept in sync. The "cluster" terminology comes from this. In a big.LITTLE system two "clusters" of CPUs [e.g. one cluster of two "big" Cortex-A-15s and one cluster of four "LITTLE" Cortex-A7s] are connected to separate AXI+ACE bus ports, and any data which is marked as outer shareable is kept in sync across the two over the ACE protocol.

    What is plugged into this outer shareable support in AXI+ACE doesn't have to be an ARM CPU cluster though - our Mali-T600 and T700 series GPUs support partial coherency ("IO Coherency"), and any hardware vendor can develop a device which support this protocol. Hence the "it depends" answer