This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

What is the difference between PoC and PoU for Cortex-A7 MPCore?

hi, experts:

ARM ARM manual introduces a concept PoC and PoU for cache maintanance operations.

Based on Cortex-A7 MPCore TRM and ARM ARM manual, i got below conclusion:

1. PoC points to external DRAM region for CA7 MPCore.

    Is it right?

2. PoU points to L1 DCache if BROADCASTINNER is low.

    Is it right?

3. What is the difference between PoC and PoU for Cortex-A7 MPCore?

    for exampe:

    DCCMVAU : DCache clean line to PoU

    DCCMVAC : DCache clean line to PoC

     They confused me!

     I don't know when to use DCCMVAC, when to use DCCMVAU.

best wishes,

  • The idea behind PoU and PoC to have way of referring to a point in the memory hierarchy in a processor agnostic way.

    PoU is the point in the memory system where the data, instruction and table walk (MMU) interfaces of this core see the same copy of a location.

    PoC is where this core and an other master (e.g. a DMA) see the same copy.

    The Cortex-A7 has separate instruction and data caches at level 1, and a unified level 2 cache*.  So PoU is the L2 cache as that is the first point all the interfaces of that core can use the same copy.  The PoC will however be the L3 memory system

    So why use PoU and PoC instead of just saying L2 and L3?  Well because not all processors have the same cache hierarchy.  Having PoU/PoC tells the processor what you are trying to do without you needing to know precisely how many levels of cache there are, or how those cases are structured.  This makes it easier to write portable code.

    When do you DCCMVAC or DCCMVAU?  Well it depends what you are trying to do.  Take the example of loading loading a program into memory.  So doing data writes to instruction memory.  Once you've loaded the program you want to push the updates at least far enough for the instruction side to see them.  So you'd clean the data cache to PoU and then invalidate the I cache.

    * The L2 is optional, but I'll ignore that for simplicity.