hi, experts:
I found ACTLR register definition is different between Cortex-A7 and Cortex-A9.
I have some questions about out cache concept in Cortex-A7.1. Some program disable outer cache by setting ACTLR[1] = 0.
So, is it only available with Cortex-A9?
In Cortex-A7 MPCore manual: ACTLR[1] is reserved, so could not disablt outer cache by this method, right?
2. Outer cache question
In Cortex-A7, L2 Cache controller is also integrated into SCU, so have not outer cache concept, right?
3. In Cortex-A7, SCTLR[2] used to control DCache enable or not.
So, if wanting to disable DCache, just set SCTLR[2] = 0, not need to disable outer cache(such as L2 Cache) anymore, right?
4. In Cortex-A7, user could not only turn on L1 DCache, and disable L2 Cache, right?
User must turn L1 DCache and L2 Cache at the same time.
And if user set SCTLR[2] = 0, then he has disabled L1 DCache and L2 Cache at the same time, right?
best wishes,
Hi Martin,
Thx for your response.
(1) I referred to TRM but it seems L2 alone can't be disabled. SCTLR.C bit will disable both L1 and L2. My purpose is to just disable L2.
Does SMP require SCU and does that in turn require L2. I thought L2 was optional even for SMP.
(2) I anyhow want to run the dual A7 SoC in UP mode. However clearing ACTLR.SMP also seems to disable caching as well. Quoting the TRM
"When coherent requests are disabled: •loads to cacheable memory are not cached by the processor."
Any ideas !
> Does SMP require SCU and does that in turn require L2. I thought L2 was optional even for SMP.
You need the L2 for SMP.
More importantly, why would you want to disable the L2 if you are in an SMP system - the performance would be terrible ...
> I anyhow want to run the dual A7 SoC in UP mode
Just put the second core to sleep on WFI - you don't need to disable the caches for this.
Pete
Hi Peter,
You are right that performance will suffer w/o L2 and that is exactly what I'm trying to measure - what is the impact of L2 on performance !
Regarding the sleep on WFI - again even if one of the cores is sleeping, the other one would still send out cache coh messages so the performance will be different than if the hardware knew not to send out those transaction over SCU.
So my end goal is to run a UP system w/o L2 caches and was wondering if we can do that on A7 at boot time.
Thx,
-Vineet
The use of snoops is controlled by the "shared" bit in the page tables - so you can just turn that off if you want to run a single core in AMP mode.
HTH, Pete
Ok thx. Any thoughts on how to go about disabling L2 cache ?
I’ve never tried on any of the newer Cortex-A ARM cores, sorry. No “normal” use case would ever do this, as performance and energy efficiency is almost always going to be better with the L2 enabled, so it may not even be possible – but I’m not sure.