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ACTLR[1] question in Cortex-A serias SOC

hi, experts:

I found ACTLR register definition is different between Cortex-A7 and Cortex-A9.

I have some questions about out cache concept in Cortex-A7.
1. Some program disable outer cache by setting ACTLR[1] = 0.

   So, is it only available with Cortex-A9?

   In Cortex-A7 MPCore manual: ACTLR[1] is reserved, so could not disablt outer cache by this method, right?

2. Outer cache question

   In Cortex-A7, L2 Cache controller is also integrated into SCU, so have not outer cache concept, right?

3. In Cortex-A7, SCTLR[2] used to control DCache enable or not.

    So, if wanting to disable DCache, just set SCTLR[2] = 0, not need to disable outer cache(such as L2 Cache) anymore, right?

4. In Cortex-A7, user could not only turn on L1 DCache, and disable L2 Cache, right?

    User must turn L1 DCache and L2 Cache at the same time.

    And if user set SCTLR[2] = 0, then he has disabled L1 DCache and L2 Cache at the same time, right?

best wishes,

Parents
  • Hi Martin,

    Thx for your response.

    (1) I referred to TRM but it seems L2 alone can't be disabled. SCTLR.C bit will disable both L1 and L2. My purpose is to just disable L2.

    Does SMP require SCU and does that in turn require L2. I thought L2 was optional even for SMP.

    (2) I anyhow want to run the dual A7 SoC in UP mode. However clearing ACTLR.SMP also seems to disable caching as well. Quoting the TRM

    "When coherent requests are disabled: •loads to cacheable memory are not cached by the processor."

    Any ideas !

Reply
  • Hi Martin,

    Thx for your response.

    (1) I referred to TRM but it seems L2 alone can't be disabled. SCTLR.C bit will disable both L1 and L2. My purpose is to just disable L2.

    Does SMP require SCU and does that in turn require L2. I thought L2 was optional even for SMP.

    (2) I anyhow want to run the dual A7 SoC in UP mode. However clearing ACTLR.SMP also seems to disable caching as well. Quoting the TRM

    "When coherent requests are disabled: •loads to cacheable memory are not cached by the processor."

    Any ideas !

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