Hi everyone
I am new to ARM and really wanted to learn about various aspects of ARM Programming .
I have basic understanding of x86 Assembly.
So,what Specifically I wanted to know is what happens when an external device triggers an interrupt .
Let me put my basic understanding on the same, which I learnt in last few days
Offset Handler =============== 00 Reset 04 Undefined Instruction 08 Supervisor Call (SVC) 0C Prefetch Abort 10 Data Abort 14 (Reserved) 18 Interrupt (IRQ) 1C Fast Interrupt (FIQ)
Whenever Interrupt comes instruction at address 18 is executed
So is it true that it is first instruction executed when interrupts comes??
Or as I read somewhere whenever interrupts comes first it moves from user mode to IRQ mode and cpsr is copied to spsr_IRQ but it happen without an instruction .
After that current instruction is replaced with a blx 0x18
blx 0x18
How and where we do need to set the stack for different mode e.g for IRQ mode and Supervisior mode??
In the brancged code
IRQ_HANDLER:
SUB lr, lr, #4
STMFD !sp {r14}
bl IRQ_handler_to_specific_device ;it will branch to actuall hander code.
LDMFD r13!,{r14} mov pc, r14
LDMFD r13!,{r14}
mov pc, r14
Is it all We need to do for setting up Basic IRQ handling ?
Also,how PIC/CPU comes to know that interrupt is coming from which device?
Thanks
Amit Singh Tomar.
"ARM is taking over the world"
Hi Amit,
A couple of other things worth noting on top of what Pete has said if you want your IRQ_handler_to_specific_device to be written in C:
1.You'd need to think about pushing r0-r3 and r12 as these may be corrupted by the called function (based on the AAPCS) - Pete alluded to this
2. You'll need to make sure the stack is 8-byte aligned prior to the BL
Also note, by default, the IRQ is non-reentrant. This means if you have multiple interrupt sources you'll need to poll them to find the actual source (ineffienent).
You can play games to support reentrant IRQs by swapping to the SVC mode before reenabling the I-bit but this gets even more messy.
Alternatively your device may have (probably has) an external interrupt controller or vectored interrupt controller to help support and prioritise multiple IRQs. Most ARMv7-A cores will probably use the ARM GIC for interrupt control which handles multiple interrupt sources and maps them onto the IRQ (especially in multi-core where you might want to select which external int is mapped to which cores IRQ).