• State Not Answered
  • Locked Locked
  • Replies 8 replies
  • Subscribers 351 subscribers
  • Views 48530 views
  • Users 0 members are here
Options
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

How AXI addressing works for fixed burst with unaligned address.

vikas verma
Please consider following example:

Data bus width = 32 bit
burst size = 4 bytes
Burst length = 3
Address = 0x02
burst type = FIXED.

Write strobes are high from byte address 0x02 to the last byte in this burst i.e. in first data beat 2 write strobes are high and in remaining data beats all 4 are high.

If this is a write transfer which byte addresses of AXI slave will be written.

I am confused between these two:
1. In first data beat, byte locations 0x02 and 0x03 will be written. In second and subsequent data beats, since all strobes are high address 0x00 to 0x03 will be written
2. In first data beat, byte locations 0x02 and 0x03 will be written. In second and subsequent data beats, since address is 0x02, only two byte for 0x02 and 0x03 will be written.

Thanks in advance.
Parents
  • 0 Arm Employee Badge
    Note: This was originally posted on 20th March 2009 at http://forums.arm.com

    Hi Vik,

    If you use a fixed burst type with an unaligned address, the address remains unaligned for the duration of the burst, so all transfers in your burst example can only transfer data on D[31:16] and only WSTRB[3:2] can be asserted.

    So it is your second description that matches what would appear on the bus.

    The spec doesn't mention burst types when describing unaligned transfers, but from the definition of "Fixed burst" in section 4.4.1, this describes the address remaining the same for all transfers in the burst, hence restricting the byte lanes available for use in each beat of the burst.

    JD
Reply
  • 0 Arm Employee Badge
    Note: This was originally posted on 20th March 2009 at http://forums.arm.com

    Hi Vik,

    If you use a fixed burst type with an unaligned address, the address remains unaligned for the duration of the burst, so all transfers in your burst example can only transfer data on D[31:16] and only WSTRB[3:2] can be asserted.

    So it is your second description that matches what would appear on the bus.

    The spec doesn't mention burst types when describing unaligned transfers, but from the definition of "Fixed burst" in section 4.4.1, this describes the address remaining the same for all transfers in the burst, hence restricting the byte lanes available for use in each beat of the burst.

    JD
Children
No data