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How AXI addressing works for fixed burst with unaligned address.

vikas verma
Please consider following example:

Data bus width = 32 bit
burst size = 4 bytes
Burst length = 3
Address = 0x02
burst type = FIXED.

Write strobes are high from byte address 0x02 to the last byte in this burst i.e. in first data beat 2 write strobes are high and in remaining data beats all 4 are high.

If this is a write transfer which byte addresses of AXI slave will be written.

I am confused between these two:
1. In first data beat, byte locations 0x02 and 0x03 will be written. In second and subsequent data beats, since all strobes are high address 0x00 to 0x03 will be written
2. In first data beat, byte locations 0x02 and 0x03 will be written. In second and subsequent data beats, since address is 0x02, only two byte for 0x02 and 0x03 will be written.

Thanks in advance.
  • 0
    Note: This was originally posted on 20th March 2009 at http://forums.arm.com

    Hi JD,

    Thanks a lot for reply. I have follow up questions on this example.
    In second and subsequent data beats all write strobes are high. Is it allowable according to AXI protocol.
  • 0
    Note: This was originally posted on 22nd March 2009 at http://forums.arm.com

    Thanks JD.
  • 0
    Note: This was originally posted on 20th March 2009 at http://forums.arm.com

    Hi Vik,

    No, all transfers in this example can only use WSTRB[3:2], because the burst is to a FIXED location.

    WSTRB bits can only be asserted for byte lanes that can contain valid data, so you cannot drive all 4 WSTRB bits high and assume the slave knows only WSTRB[3:2] are valid because of the address used.

    Your use of an unaligned address for this FIXED burst means all transfers in the burst have the same byte lane restriction.

    JD
  • 0
    Note: This was originally posted on 20th March 2009 at http://forums.arm.com

    Hi Vik,

    If you use a fixed burst type with an unaligned address, the address remains unaligned for the duration of the burst, so all transfers in your burst example can only transfer data on D[31:16] and only WSTRB[3:2] can be asserted.

    So it is your second description that matches what would appear on the bus.

    The spec doesn't mention burst types when describing unaligned transfers, but from the definition of "Fixed burst" in section 4.4.1, this describes the address remaining the same for all transfers in the burst, hence restricting the byte lanes available for use in each beat of the burst.

    JD
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    Hi all

    But here he has mention transfer size 4 bytes i.e. 32 bits at every beat needed to be transferred ???

    so had VIk  mentioned wrong data size and is it protocol violation

    Vir

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    Can anyone clear the doubt of Virat Sharma, I have the same question. set values we are driving are wrong 

    Set of values, we are driving, are wrong or right

    If right what will be the number of valid bytes lane for each transfer and what will be those byte lanes. 

    (If we are instructing to get 32bit data and getting only 16bits of it so either this scenario is wrong or AXI protocol supports an inefficient scenario. ) 

    I am not expert but want to understand all these things 

  • 0

    Hi Vikas,

    Your second assumption is correct.

    In fixed type, lane will not changed between beats.

    You can refer this from AXI4 spec at A3.4.2 Pseudocode description of the transfers.

    so if you calculate lower and upper lane for 1 to n beats, these will remain same.