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How AXI addressing works for fixed burst with unaligned address.

vikas verma
Please consider following example:

Data bus width = 32 bit
burst size = 4 bytes
Burst length = 3
Address = 0x02
burst type = FIXED.

Write strobes are high from byte address 0x02 to the last byte in this burst i.e. in first data beat 2 write strobes are high and in remaining data beats all 4 are high.

If this is a write transfer which byte addresses of AXI slave will be written.

I am confused between these two:
1. In first data beat, byte locations 0x02 and 0x03 will be written. In second and subsequent data beats, since all strobes are high address 0x00 to 0x03 will be written
2. In first data beat, byte locations 0x02 and 0x03 will be written. In second and subsequent data beats, since address is 0x02, only two byte for 0x02 and 0x03 will be written.

Thanks in advance.
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    Hi Vikas,

    Your second assumption is correct.

    In fixed type, lane will not changed between beats.

    You can refer this from AXI4 spec at A3.4.2 Pseudocode description of the transfers.

    so if you calculate lower and upper lane for 1 to n beats, these will remain same.

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    Hi Vikas,

    Your second assumption is correct.

    In fixed type, lane will not changed between beats.

    You can refer this from AXI4 spec at A3.4.2 Pseudocode description of the transfers.

    so if you calculate lower and upper lane for 1 to n beats, these will remain same.

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