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Setting up TCM Memory in ARM926EJ-S

bekiricli bekiricli
Note: This was originally posted on 20th October 2008 at http://forums.arm.com

Hi all,

I am currently trying to turn on TCM in ARM926EJ-S where there is 64K for ITCM, DTCM and internal SRAM.
I have decided to use it as:
32K ITCM
16K DTCM
16K SRAM

Therefore I thought I can use the memory from 0x30000 to 0x304000 no matter what, and set my stack pointer and exception+interrupt vectors to this location.
But as soon as I turn on TCM, the data in this memory is gone.
Does this make sense, or am I doing something wrong?

Here is how I do my TCM initialization:
HW_UINT32  dtcm, itcm;
HW_UINT32  enable_memory_sharing;

#define   HW_TCM_ENABLE  0x1
#define   HW_ITCM_SIZE_32K   6
#define   HW_DTCM_SIZE_16K  5

  enable_memory_sharing = 0;

 
  __asm__ __volatile__("MRC p15, 0, %0, c9, c1, 0":"=r"(dtcm));
  dtcm  |= ( 0x10104000 | (HW_DTCM_SIZE_16K << 2) | HW_TCM_ENABLE );
  __asm__ __volatile__("MCR p15, 0, %0, c9, c1, 0"::"r"(dtcm));

  enable_memory_sharing |= AT91C_CCFG_DTCM_SIZE_16KB;

  __asm__ __volatile__("MRC p15, 0, %0, c9, c1, 1":"=r"(itcm));
  itcm  |= ( 0x10108000 | (HW_ITCM_SIZE_32K << 2) | HW_TCM_ENABLE );
  __asm__ __volatile__("MCR p15, 0, %0, c9, c1, 1"::"r"(itcm));

  enable_memory_sharing  |= AT91C_CCFG_ITCM_SIZE_32KB;
 
  AT91C_BASE_CCFG->CCFG_TCMR  = enable_memory_sharing;

Regards,
Bekir
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  • 0
    Note: This was originally posted on 22nd October 2008 at http://forums.arm.com

    Hi all,

    I got it finally working but the performance values say that I am doing something wrong.
    Maybe you guys can give me a hint.

    I am setting my instruction TCM Base as 0x10108000.
    Would it make sense to have a performance difference between these two accesses?:
    1- via 0x100000
    2- via 0x0x10108000

    The reason I am trying to use TCM is the fact that it has the same speed as the caches. But somehow, my code (which is in ITCM) becomes faster, when I turn on the cache at 0x100000.
    Is this in anyways logical?

    Regards,
    Bekir
Reply
  • 0
    Note: This was originally posted on 22nd October 2008 at http://forums.arm.com

    Hi all,

    I got it finally working but the performance values say that I am doing something wrong.
    Maybe you guys can give me a hint.

    I am setting my instruction TCM Base as 0x10108000.
    Would it make sense to have a performance difference between these two accesses?:
    1- via 0x100000
    2- via 0x0x10108000

    The reason I am trying to use TCM is the fact that it has the same speed as the caches. But somehow, my code (which is in ITCM) becomes faster, when I turn on the cache at 0x100000.
    Is this in anyways logical?

    Regards,
    Bekir
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