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Abort some questions of arm interrupt

Note: This was originally posted on 20th June 2008 at http://forums.arm.com

I try to understand arm interrupt,there are some questions I don't know,
  1.   Why the nested interrupt has to switch out of irq mode to svc mode?  I think  it only pushes the r14_irq into the irq stack.
   2.    The basic difference between a reentrant interrupt handler and a nested interrupt han-dler is that the interrupts are reenabled early on in the reentrant interrupt handler, which can reduce interrupt latency.
    I can't understand that ?

   thanks!
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  • Note: This was originally posted on 27th June 2008 at http://forums.arm.com

    Sunmoon,

    For the first definition (checking for new interrupts before returning), Cortex-M3 already deals with this automatically in hardware, and will perform a "tail-chain" from the end of one interrupt to the entry of another without performing unstacking and restacking.

    The second definition is less useful on a closed/embedded platform; the typical example of this type of chaining used to be the DOS TSR (terminate and stay resident) handlers for things like adding special key bindings e.g. "holding CTRL+ALT+A+B brings up my special program". In this scenario, the TSR would replace the keyboard interrupt vector with its own address, giving itself the chance to check for the magic keysequence, but would then chain onto the original handler if it didn't find what it was looking for. This kind of system may also exist where multiple peripherals share a single interrupt line/handler.

    Replacing the interrupt vector on Cortex-M3 is simply a matter of changing the pointer value in the vector table in memory, though on most MCUs this would likely also require the vector table to be relocated to RAM first.

    hth
    s.
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  • Note: This was originally posted on 27th June 2008 at http://forums.arm.com

    Sunmoon,

    For the first definition (checking for new interrupts before returning), Cortex-M3 already deals with this automatically in hardware, and will perform a "tail-chain" from the end of one interrupt to the entry of another without performing unstacking and restacking.

    The second definition is less useful on a closed/embedded platform; the typical example of this type of chaining used to be the DOS TSR (terminate and stay resident) handlers for things like adding special key bindings e.g. "holding CTRL+ALT+A+B brings up my special program". In this scenario, the TSR would replace the keyboard interrupt vector with its own address, giving itself the chance to check for the magic keysequence, but would then chain onto the original handler if it didn't find what it was looking for. This kind of system may also exist where multiple peripherals share a single interrupt line/handler.

    Replacing the interrupt vector on Cortex-M3 is simply a matter of changing the pointer value in the vector table in memory, though on most MCUs this would likely also require the vector table to be relocated to RAM first.

    hth
    s.
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