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If I recall correctly, a nested interrupt handler allows a higher-priority interrupt to interrupt it. For example, you might want a timer interrupt to have higher priority than a UART interrupt, because what you are doing in the timer requires hard real-time guarantees on latency. In this model, an interrupt cannot interrupt the handler for itself.In a re-entrant interrupt routine, a second interrupt of the same type can interrupt processing of the first one. This is rarer, because if the interrupt is that important, you probably need to service the first one anyway. Re-entrant code is more difficult to write and debug, since it will often require access to the same data structures as the interrupted interrupt handler. It also allows unbounded stack growth if the interrupts come in too fast to handle.
Sean,...............Interrupt nesting: interrupt A can preempt handling of interrupt B; both interrupt A and interrupt B's handlers can be "active" at the same time.Re-entrant interrupt: interrupt A can preempt handling of interrupt A; interrupt A's handler can be active concurrently with itself...................hths.
Sean,Interrupt chaining: (an overloaded term) means one of two things; firstly checking for a new pending interrupt before returning from interupt context (i.e. a scenario which would could waste time by unstacking and then straight away restacking the same registers); or secondly, linking handlers together (typically by replacing the interrupt vector with the new handler to run, followed by the new handler calling the original handler). I assume you mean the first.hths.
Sunmoon,For the first definition (checking for new interrupts before returning), Cortex-M3 already deals with this automatically in hardware, and will perform a "tail-chain" from the end of one interrupt to the entry of another without performing unstacking and restacking.The second definition is less useful on a closed/embedded platform; the typical example of this type of chaining used to be the DOS TSR (terminate and stay resident) handlers for things like adding special key bindings e.g. "holding CTRL+ALT+A+B brings up my special program". In this scenario, the TSR would replace the keyboard interrupt vector with its own address, giving itself the chance to check for the magic keysequence, but would then chain onto the original handler if it didn't find what it was looking for. This kind of system may also exist where multiple peripherals share a single interrupt line/handler.Replacing the interrupt vector on Cortex-M3 is simply a matter of changing the pointer value in the vector table in memory, though on most MCUs this would likely also require the vector table to be relocated to RAM first.hths.
Hi sim, For Interrupt nesting, I don't think interrupt A and interrupt B's handlers can be "active" at the same time. interrupt B must wait for returning by interrupt A if no interrupt occurs.