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Cortex-A7 cache line size

haooo

Hi All, 

when I read the ARM® Cortex -A Series Programmer’s Guide for ARMv7-A

I found that at page 8-12 Tabel 8-1 Cache features of Cortex-A series processors (continued)

there is a field say that Cortex-A7 cache line(words) is 8 and cache line(bytes) is 64  

I'm confused about 1 word = 4 byte, but it seems that 1 word is 8 byte here 

Is that a mistake or there is something I missed ?

And another question is why the Cortex-A12's  cache line(words) is  blank ?

Thanks for you guys help !

Regards,

Matt

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  • 0

    I rate it a typo given the age of the document.
    The TRM for the CA7 says:


    The L1 instruction memory system has the following features:
    • Instruction side cache line length of 32-bytes.

    And:
    [3:0] IminLine Log2 of the number of words in the smallest cache line of all the instruction caches that the processor controls.
    0x3  Smallest instruction cache line size is 8 words.

    For data:

    The L1 data memory system has the following features:
    • Data side cache line length of 64-bytes.

    [19:16] DminLine Log2 of the number of words in the smallest cache line of all the data and unified caches that the processor
    controls:
    0x4  Smallest data cache line size is 16 words.

Reply
  • 0

    I rate it a typo given the age of the document.
    The TRM for the CA7 says:


    The L1 instruction memory system has the following features:
    • Instruction side cache line length of 32-bytes.

    And:
    [3:0] IminLine Log2 of the number of words in the smallest cache line of all the instruction caches that the processor controls.
    0x3  Smallest instruction cache line size is 8 words.

    For data:

    The L1 data memory system has the following features:
    • Data side cache line length of 64-bytes.

    [19:16] DminLine Log2 of the number of words in the smallest cache line of all the data and unified caches that the processor
    controls:
    0x4  Smallest data cache line size is 16 words.

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