Hello there,
I want to enable MMU and Cache to improve the performance of my arm cortex-A5 core.
I have gone through the Reference manual of arm cortex a5 and found the below step to enable mmu and cache
Steps :
1.Disable cache, branch predictors
2. Invalidate cache and TLB
3. set translation table entries , point ttbr register to translation table.
4.enable cache, branch predictor
5. enable MMU.
Queries
1. I need help to understand how the translation table entries are defined.. If i choose 1MB section option then
how can i make entry for External flash memory which is of 16MB.
Here we have different memory regions, internal Ram(1MB), internal flash(4MB), External flash(16MB) and so on..
How can i define translation table entries for the above mentioned memory regions.
2. Translation tables are stored in main memory, here main memory is RAM ???
3 How can we check all the above steps working or not in trace32 ??
by executing the command cache.view i am able to see the cache content but i am unable to understand it.
Thanks in Advance.
ZbinAhmed
Hi Van,
I have made translation table entries, flashed the app and debugging it. And when i enable mmu, translation/section fault occurs.
The memory dump is getting locked ( all ? marks).
I am using 1MB section, so here we will have 4096 entries for L1 translation table.
Can i use any 'x' entry to hold information about any 'y' 1MB section ???
Way 1: starting from the address 0x0000_0000 to 0xFFFF_FFFF
entry[0x000] = sect[0x00000000 - 0x000FFFFF] //section 1
entry[0x001]= sect[0x00100000 - 0x001FFFFF] //section2
entry[0x002]= sect[0x00200000 - 0x002FFFFF] //section3
Way 2:
entry[0x000] = sect[0x18F00000 - 0x18FFFFFF]
entry[0x001]= sect[0x19000000 - 0x190FFFFF]
entry[0x002] = sect[0x19100000-0x191FFFFF]
Are the above mentioned ways valid ???
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0333h/Babicjaf.html
6.9.3. Translation fault
There are two types of translation fault:
A section translation fault occurs if:
The TLB tries to perform a page table walk but the page table walk is disabled by one of the PD0 or PD1 bits. For more details, see Hardware page table translation.
The TLB fetches a first level translation table descriptor, and this first level descriptor is invalid. This is the case when bits[1:0] of this descriptor are b00 or b11.
1. I have checked, It is not because of PD0 bit.
2. And for the underlined point, is it referring to 1st two lower bits of entry ?? ,
because i am using section type entry, the lower 2 bits are "10"
Can you please suggest something.
Thanks
Can you send the code with MMU configuration to my email (you can find email in my contacts)?