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VMSAv8-64 and spinlock

Ciro Donnarumma

Hi,

I'm trying to implement a spin-lock to synchronize the execution of all cores Cortex-A53 on my Xilinx-ZCU102 board, but I have some issues maybe due to a wrong configuration of the VMSA and cache coherence.

I'm writing bare-metal code, without the bsp provided by Xilinx. My software system is composed by:

  • The FSBL and PMUFW provided by Xilinx;
  • Bootloader bl31 obtained by the compilation of Arm Trusted Firmware for the zynqmp platform;
  • My code;

I use xsct tool to download over JTAG and execute the software. The steps that i follow to boot are:

  1. Download and run the PMUFW.
  2. Download and run the FSBL for 5 seconds.
  3. Download bl31 at address 0x1000 (DEBUG mode) and my code at address 0x8000000 (the entrypoint of my software is 0x8000000) and run.

The boot completes correctly and my code takes the control in EL2-NS AArch64 execution state, so I create the translation table and configure the VMSA in this way:

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TCR_EL1 = 0000001225192519
MAIR_EL1 = 00000004bb4400ff
TTBR0_EL1 = 000000000800a000
TTBR1_EL1 = 0000000000000000
SCTLR_EL1 = 00c01805
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

As next action I ask to ATF, using the SMC CPU_ON, to launch the other cores at address 0x8000000. All the secondary cores start and they do the same configuration of the VMSA.

Following, there is an infinite loop in which the CPUs acquire a spin-lock, print a message over UART and release the spin-lock.

The problem is that only the CPU 0 can acquire the spin-lock. If I stop the execution after the spin-lock release of the CPU0, I can see that the lock variable for CPU0 is correctly 0 (unlockd), but the other CPUs see the value 1 (locked). So, if i try to dump he memory of the lock, using the xsct tool, the variable becomes 0 also for another CPU and resuming the execution, two CPUs can acquire and release the spin-lock.

Is this a cache coherence problem?

 

Other useful details are the following:

  • The spin-lock functions are implemented in this way:

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FUNCTION(spinlock_acquire)
push_volatile_registers sp
mov x29, sp
sevl
loop:
wfe
ldaxr w1, [x0]
cbnz w1, loop
mov w1, #1
stxr w2, w1, [x0]
cbnz w2, loop
pop_volatile_registers sp
ret
ENDFUNC(spinlock_acquire)
FUNCTION(spinlock_release)
stlr wzr, [x0]
ret
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

  • The lock variable is at address 0x0000000008014000 (bss section).
  • My translation table is the following:

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DESCRIPTOR: level 1 index: 000 --> 0000000000000e21 (0000000000000000)
DESCRIPTOR: level 1 index: 001 --> 0000000040000e21 (0000000040000000)
DESCRIPTOR: level 1 index: 002 --> 0060000080000405 (0000000080000000)
DESCRIPTOR: level 1 index: 003 --> 800000000800b003 (000000000800b000)
DESCRIPTOR: level 2 index: 000 --> 00600000c0000405 (00000000c0000000)
DESCRIPTOR: level 2 index: 001 --> 00600000c0200405 (00000000c0200000)
DESCRIPTOR: level 2 index: 002 --> 00600000c0400405 (00000000c0400000)
DESCRIPTOR: level 2 index: 003 --> 00600000c0600405 (00000000c0600000)
DESCRIPTOR: level 2 index: 004 --> 00600000c0800405 (00000000c0800000)
DESCRIPTOR: level 2 index: 005 --> 00600000c0a00405 (00000000c0a00000)
DESCRIPTOR: level 2 index: 006 --> 00600000c0c00405 (00000000c0c00000)
DESCRIPTOR: level 2 index: 007 --> 00600000c0e00405 (00000000c0e00000)
DESCRIPTOR: level 2 index: 008 --> 00600000c1000405 (00000000c1000000)
DESCRIPTOR: level 2 index: 009 --> 00600000c1200405 (00000000c1200000)
DESCRIPTOR: level 2 index: 010 --> 00600000c1400405 (00000000c1400000)
DESCRIPTOR: level 2 index: 011 --> 00600000c1600405 (00000000c1600000)
DESCRIPTOR: level 2 index: 012 --> 00600000c1800405 (00000000c1800000)
DESCRIPTOR: level 2 index: 013 --> 00600000c1a00405 (00000000c1a00000)
DESCRIPTOR: level 2 index: 014 --> 00600000c1c00405 (00000000c1c00000)
DESCRIPTOR: level 2 index: 015 --> 00600000c1e00405 (00000000c1e00000)
DESCRIPTOR: level 2 index: 016 --> 00600000c2000405 (00000000c2000000)
XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

Can someone help me?

 

Best regards,

Ciro

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