Dear experts,
I'm going to implement multi-core(4 cortex-a53) in my private OS. I have an issue which needs your confirmation.
Q. When core0 invalidates the L1-cache and L2-cache at VADDR(Cached), Can other cores get the right data at VADDR ?
For example,
core0 is waiting for DMA transfer at address 0x100000, after DMA finishing, core0 invalidates 0x100000.
So core0 can access 0x100000 and get the right data, how about other cores ? is the data right when other cores access ?