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Dear experts,
I'm going to implement multi-core(4 cortex-a53) in my private OS. I have an issue which needs your confirmation.
Q. When core0 invalidates the L1-cache and L2-cache at VADDR(Cached), Can other cores get the right data at VADDR ?
For example,
core0 is waiting for DMA transfer at address 0x100000, after DMA finishing, core0 invalidates 0x100000.
So core0 can access 0x100000 and get the right data, how about other cores ? is the data right when other cores access ?
BTW, CPUECTLR.SMPEN=1
I think after you invalidate an address in D caches, eg. "DC IVAC, xt" to the Point of Coherency, you make the line including the address invalid in all the D caches up to the Point of Coherency (PoC is the L3 cache if you have the L3 cache or the main memory if you don't have the L3) . If the line was only in the caches up to PoC (L1 through L2 D caches), that is in Modified with respect to L3 (or the main memory) you will lose the line.
"ARM Cortex-A Series Programmer’s Guide for ARMv8-A" has a chapter 11 and 14 addressing your questions on what Cache Maint. Operations (CMOs) get broadcast to other cores in Inner/Outer Shareable Domains.
In case of "DC IVAC, xt" it gets broadcast to the cores in Inner and Outer Shareable Domains.
Thank you very much for your reply, your comment is very helpful for me.Thanks again.