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Forums

  • Operating Systems forum

    The latest forum discussions for all Arm technology relating to Operating Systems (OS)
    272 questions
    Cantaff0rd
    UEFI variables from UEFI shell 2 months ago
  • Servers and Cloud Computing forum

    The latest forum discussions about the Arm Servers and Cloud Computing ecosystem for cloud native edit to cloud application development and deployment.
    101 questions
    romain beurdouche
    RE: ArmRAL: Wrong usage of k0 in LDPC rate matching 5 months ago
  • SoC Design and Simulation forum

    The latest forum discussions for community-based support for System-on-Chip (SoC) and Arm simulation models.
    707 questions
    Firoz M L
    In CHI how the Slave side is giving the L-Credits to the Master Side 1 day ago
  • SystemReady Forum

    The SystemReady forum covers all aspects of the Arm SystemReady compliance program, including associated specifications (BSA, SBSA, BBR), Architecture Compliance Suite (ACS) testing, and implementation considerations for pre-silicon and SystemReady bands.
    15 questions
    vstehle
    RE: How to run ARM ACS 4 months ago Arm Employee Badge
  • 恩智浦汽车电子MCU讨论区博

    4 questions
    Song Bin 宋斌
    RE: [TRK-KEA64使用经验分享] 开箱体验 亮瞎我的双眼 over 9 years ago Arm Employee Badge
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All questions in this Community
  • Answered

    Hardfault because of decompression when using FreeRTOS +1

    • M7
    • Scatter Loading
    • C
    2089 views
    3 replies
    Latest over 1 year ago
    by TheSemaphoreNoob
  • Suggested Answer

    Zynq™︎ UltraScale+™︎ (Cortex-A53) deadlock 0

    • Cortex-A53
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    1 reply
    Latest over 1 year ago
    by Zhifei Yang Arm Employee Badge
  • Suggested Answer

    Dual core Cortex-A7 L2 cache lockdown or partitioning 0

    1523 views
    1 reply
    Latest over 1 year ago
    by Zhifei Yang Arm Employee Badge
  • Suggested Answer

    Is number of instructions a valid measurement for realm VM in FVP +1

    2098 views
    2 replies
    Latest over 1 year ago
    by Sina Abdollahi
  • Answered

    In A53, is the L1 D cache way allocation random? 0

    1981 views
    3 replies
    Latest over 1 year ago
    by User_0182
  • Not Answered

    Keil generating corrupted output files 0

    • Keil uVision
    • stm32cube
    • STM32G0
    526 views
    0 replies
    Started over 1 year ago
    by Daniel Pecci
  • Answered

    What does "the architecture permits caching of GPT information in a TLB" mean? 0

    • virtualization
    • Security
    • Memory Management Unit (MMU)
    • TrustZone
    1723 views
    2 replies
    Latest over 1 year ago
    by Ming Gao
  • Not Answered

    Internal parameter error in keil c 0

    772 views
    1 reply
    Latest over 1 year ago
    by Volter_1122
  • Answered

    What does "permits caching of GPT information in a TLB" mean? +1

    • AArch64
    • Cortex-A
    • TrustZone
    1347 views
    1 reply
    Latest over 1 year ago
    by Ronan Synnott Arm Employee Badge
  • Suggested Answer

    Online Student Resources for "Digital-Signal-Processing-using-Arm-Cortex-M-based-Microcontrollers: Theory-and-Practice" 0

    • DSP
    • Digital-Signal-Processing-using-Arm-Cortex-M-based-Microcontrollers
    • arm-dsp-textbook
    • Online Student Resources
    • textbook
    • Digital Signal Processing using Arm Cortex M based Microcontrollers
    1652 views
    1 reply
    Latest over 1 year ago
    by Ronan Synnott Arm Employee Badge
  • Answered

    Virtual IRQ and IRQ handling +1

    2703 views
    4 replies
    Latest over 1 year ago
    by sumit negi
  • Suggested Answer

    Running C++/CLI code on Windows arm64: mscoree.dll missing 0

    • Windows
    1961 views
    2 replies
    Latest over 1 year ago
    by ndvn
  • Answered

    Set Mali GPU operating frequency 0

    • Android
    • Mali GPU Tools
    • Mali-GPU
    1994 views
    1 reply
    Latest over 1 year ago
    by Peter Harris Arm Employee Badge
  • Suggested Answer

    [AXI] Can AxUser change when valid is asserted 0

    • AXI4
    1964 views
    3 replies
    Latest over 1 year ago
    by Martin Weidmann Arm Employee Badge
  • Not Answered

    Arm Cortex M7 SWD (Serial Wire Debug) read DPACC DPIDCODE failed 0

    • DPACC
    • Cortex M7
    • SWD
    814 views
    0 replies
    Started over 1 year ago
    by Hsu HANWENHSU
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