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Suriya Gunasekaran

STMicroelectronics speakers

Name Profile

Vinay Thapliyal
Group Manager- Technical Marketing,
Southeast Asia & India
Microprocessors Product Group   
With more than 25 years of experience in the semiconductor industry, Vinay Thapliyal has worked in various functions of Technical Marketing, Embedded Designs and Applications on multiple projects for the emerging markets in the segments of Industrial, Consumer and Automotive. He is presently the marketing in-charge of microprocessor product group for South-East Asia, India and ANZ regions.

Subham Boharapi
Tech Leader,
General Purpose Microcontrollers
Sub-Group
Shubham is currently working as a tech leader in STMicroelectronics and has Industry experience over 13 years as a developer and project leader on electronics systems for multi-disciplinary domains (HW & SW). He has a deep understanding of MCU architectures, peripherals, and development tools, dedicated to providing exceptional technical support and guidance to customers in their MCU-based projects.
He is passionate about assisting customers in achieving their MCU-based project objectives and delivering exceptional support throughout their development journey.
His main areas of expertise are Microcontrollers of various core, Embedded Software, Wireless stack developer, HMI, and Graphics.

Krishan Solanki
Staff Engineer,
General Purpose Microcontrollers
Sub-Group
Krishan Kumar Solanki, a seasoned professional with over 17 years of experience in Embedded system design and support. He has been a valuable member of the Embedded Applications support team at STMicroelectronics India for the past 12 years. Krishan's expertise spans across various Microcontroller cores, including ARM7, ARM CM0 to CM7, MSP430, 8051, PIC, AVR, and more.
Throughout his career, Krishan has contributed to a wide range of applications, demonstrating his versatility and adaptability. He has successfully worked on projects involving IoT, BLE, NFC, Automotive, Motor Control, Inverter, Metering, Industrial and Home Automation, and various other domains. Krishan's current focus lies in the realms of security and AI applications.

Sanjay Kumar
SoC Physical Design Manager,
General Purpose Microcontrollers (GPM)- MDG
Sanjay is currently managing the SoC Physical Design team for General Purpose Micro (GPM) products in ST, Greater Noida. He has been involved in multiple successful tape-outs. As part of SoC Physical Design, he has driven key initiatives in implementation of high-speed complex subsystems, and critical IPs for best-in-class power, performance, and area while also having good management experience. He has multiple publications/presentations and tech poster in his name in various forums.
Mansi Chadha
Digital IP Verification Manager,
General Purpose Microcontrollers
(GPM)-MDG
Mansi is currently managing the Digital IP Verification team for General Purpose Micro (GPM) products in ST, Greater Noida. Over 19 years in verification, she has extensively worked at different levels (IP/SubSystem/SoC) including Verification IP development.
Her expertise in Verification Methodologies and Verification Milestones enabled her to execute & manage multiple metric driven verification projects working with global teams.
She has Having deep experience with verification technologies like UVM, SystemVerilog, C, C++, SystemC, Transaction Level Modeling (TLM), Object-Oriented concepts and Formal Verification and has made multiple technical publications, articles, and patents.
Abhinav Gaur
SoC Verification Manager,
General Purpose Microcontrollers
(GPM)-MDG
Abhinav is currently managing the SoC Verification team for General Purpose Micro (GPM) products in ST, Greater Noida. He has extensively worked on MCUs and MPUs across Industrial & Automotive applications and contributed to multiple successful tape-outs. He has driven key initiatives in testbench standardization, regression automation, coverage, GLS, etc. and is an expert in formal verification establishing many areas of its application. He has a total of 22 publications/presentations in various forums and 2 patents in the area of functional safety.
Akhil Garg
SoC DFT (Design for Test) Manager                
General Purpose Microcontrollers
(GPM)-MDG
Akhil currently manages the SoC DFT team for General Purpose Micro (GPM) products in ST, Greater Noida. He has 19 year experience working extensively on different aspects of DFT & Test. He holds an MS(R) degree from Indian Institute of Technology, Delhi. His research interests are in the field of Digital / Analog DFT and Silicon debug. He has a total of 11 publications in IEEE conferences 12 patents in the area of design for test.
Pushkar Sareen
SoC Design Architect         
General Purpose Microcontrollers
(GPM)-MDG
Pushkar is currently engaged in Design Architecture activities for General Purpose Micro (GPM) products in ST, Greater Noida. He has worked at IP and SOC level in design, architecture & specifically in performance analysis also. He also has rich experience in SoC Verification. His key interest is Performance Architecture and has driven many performance enhancement initiatives in various SoCs. He has 2 patents and 6 publications in the field on Security and SoC Performance Analysis.
Ashish Kumar Sharma
IP Sourcing- MDG GPM IDC 
Ashish is managing IP Sourcing for General Purpose Micro (GPM) products in ST, Greater Noida. With 22+ years of experience, he has experience doing things in verification, design, architecture domain from scratch. Has deep expertise in architecture definition, planning, execution, resource management, risk mitigation, strategy loop development and deployment, cross functional working with various stakeholders, customer interaction, managing teams across different sites.
A recognized leader is a pro on cross vertical coherence, diversity, collaborative leadership and deploying processes to attain reliability-repeatability-consistency and sustainability.
Mukesh Chopra
Director
Microcontrollers & Digital ICs Group (MDG) R&D India
With 20+ years in semiconductor industry (VLSI & Software), Mukesh has strong Leadership acumen having a rich experience across SOC development cycle including SOC design & verification, Subsystem/IP development, System level design, Design methodology & Foundation library development. He has contributed to products ranging from 0.18um to 5nm technologies in consumer, automotive, industrial & storage domains. In addition, he has actively participated in International Standardizing bodies. Led several cross-functional and global task forces, driven EDA partnerships to solve complex organizational and technical challenges.
Nabarun Dasgupta 
Group Manager – Industrial and Power
System Application and Integration Lab
System Research and Applications Group
Nabarun Dasgupta has been working for STMicroelectronics since 1999. With Overall 3 decades of Industry experience, he has expertise and interests in the areas of Electronic Systems design, Embedded systems and Firmware, Power electronics and Drives, Industrial control, and digital communication. He has extensive experience as a team lead focusing on product, people, project management and as a mentor to young engineers and Interns.He is a hands-on designer, currently creating solutions for industrial automation and motor drives. His team has developed several advanced system solutions for digital power, E-mobility, and Industrial applications. 
Sridhar Ethiraj
Senior Manager – Technical Marketing & Applications, India 
General-Purpose Microcontrollers Sub-Group
With more than 20 years of experience in Semiconductor Industry as Field Application Engineer, Sridhar Ethiraj supported customer product design and development based on STM32 / STM8 Microcontrollers for distinct applications. Presently, he is responsible for technical marketing & Applications in India for STM32 microcontrollers. Sridhar Ethiraj has rich working experience with Cortex-M based Microcontrollers, Renesas Microcontrollers & 8051 based Microcontrollers. He has lots of hands-on experience in working with different hardware debugger tools, IDE compilers and assemblers.
Ranajay Mallik
Senior Principal Engineer
System Research and Applications
Ranajay is an experienced power electronics and system design professional with several patents and publications. His primary responsibilities  are exploring and implementing new topologies in the field of power conversion, digital power conversion, alternate energies and industrial electronics. High power density resonant power supplies are his focus areas utilizing traditional and wide band gap semiconductors. Efficient magnetics design for power conversion is an acquired expertise over the last several years. He also drives industry and university partnerships for collaborative research work in the domain of power electronics and control systems for power electronics.
Hong Shao Chen
Marketing and Application Manager
South Asia and India
MEMS Sensor Group
Hong Shao Chen has been working in MEMS sensor application for more than 18 years in ST Microelectronics Pte. Ltd, Singapore. Before dedicated into MEMS technology, he has more than 13 years of R&D experience in Power Electronics, RF and Mixed-Signal System hardware & software design.

Arm speakers

Name  Profile

Ish Dham
Distinguished Engineer            Architecture and Technology     		 Ish is a Distinguished Engineer at Arm in the Architecture and Technology group.  With a background in Computer Science, Ish comes with a strong passion for Computer Architecture.  He has been involved in the design and validation of high quality processors and SoCs spanning multiple domains.  Currently, Ish is driving the machine readable specifications strategy for Arm architecture.  As part of this strategy, Arm is endeavoring to provide as much of the specification as possible in a structured machine readable fashion besides the standard document format.  Through this, we hope to enable innovation in both hardware and software design that relies on accurate interpretation of the architecture.

Sahana Devaiah Barike
Principal Field Application Engineer
Sales and Partner Enablement
 Sahana Devaiah Barike has 13+ years of experience in the Semiconductor industry. She has bachelor’s degree in Electronics and Communications from VTU and has vast experience in various roles in the industry. She started her career as a software engineer in Pathparter Technologies and worked on multiple multimedia video codecs like MPEG4, H.264, HEVC etc.
She has 5+ years of experience in the role of Field Application Engineer and is with Arm for more than a year now. Prior to Arm, she was working with Xilinx as a FAE. She has experience working on Arm processors, SoC and various Arm tools.
Desikan Srinivasan
Director of Engineering
CE-CPU
 Desikan Srinivasan works as Director of Engineering at Arm. He has been working on the design verification domain for more than 25 years. He is currently managing a part of CPU design verification team in Arm Bangalore and has been with Arm for more than 16+ years. He had worked for IBM and Transwitch in the past.
Prasanth Pulla
Senior Principal CPU Validation Architect
Architecture and Technology 
 Prasanth Pulla is a Senior Principal CPU Validation Architect in the Architecture and Technology group at Arm. He has been part of the Silicon and Firmware industry for 19 years. He joined Arm 6 years ago and has been part of multiple projects spanning embedded hardware, Firmware and Operating systems at Arm. He is the author of the Arm BSA (Base System Architecture) specification. He has contributed to multiple Arm System compliance projects which are open source and available on Github. His expertise is Arm based Servers, boot loaders, embedded firmware and operating system internals.
Sharad Kumar
Engineering Director
SE SoC Engineering
 Sharad is leading teams for front-end design, verification and silicon validation for ARM’s flagship SoCs.  He has 25 years of industry experience and has a BE and MS degrees in Computer Engineering.  He is a senior member of IEEE and a past awardee of the Mahboob Khan Industry liaison award given by Semiconductor Research Corporation (SRC) for industry-academic research collaboration.
Vamsikrishna Dabbara
Principal Engineer
SE SoC Engineering
 Vamsikrishna works as Principal DFT Engineer at Arm. His expertise is into DFT(Design For Test) domain, where the required infrastructure(MBIST/BSCAN/SCAN etc.) are added into the design to make sure the silicon is manufacturing defect free by testing it on ATE by leveraging the infrastructure being added into the design while development. Before joining Arm he had worked at Intel, Microsemi and Sifive.
Parivesh Chandra Gupta
Principal Engineer
SE SoC Engineering
 Parivesh Chandra is a semiconductor professional with a background in Electronics and Communication Engineering, Graduating from NIT Warangal in 2006.He has over 17 years of expertise in the design and verification of complex electronic designs. He is specialized in CPU and processor complex verification, with a track record spanning over 15 years in this field. With a deep understanding of ARMv8/ARM64 and ARMv9 architectures, he possess extensive knowledge in this domain. He has hands-on experience in verifying major coherency protocols and are well-versed in x86 core, North Bridge, and South Bridge architectures.
Having been involved in over 10 tape outs across multiple products, he has a strong background in the end-to-end design and development process. In addition to verification prowess, he has also been involved in the complete lifecycle of IP development, starting from specification, and culminating in RTL implementation.
Pratik Bhattacherjee
Principal Engineer
Architecture and Technology 
With over 12 years of experience in Processor/CPU verification, Pratik’s expertise lies in working with diverse Application (A-Class) and real-time (R-Class) processors. His background includes extensive work in CPU Architecture Compliance and System Compliance, where he has worked with various Arm IPs and third-party IPs. He is dedicated to ensuring high-quality processor verification and contributing to the advancement of cutting-edge technologies.
Dr. Pammi Sesha Srinivas 
Director Engineering
SE SoC Engineering
Dr. Pammi Sesha Srinivas works as Director Engineering at Arm. With 24 + years of experience, Srinivas was instrumental in forming successful teams for post Si Validation of SoC in the areas of server and client computing, accelerator subsystems, smart NICs, IPU and automotive micro controllers for companies like Intel, Infienon. He holds a master’s degree from IISc and PhD from SVYASA university.
Basab Kundu
Senior Principal Engineer
SE SoC Engineering
Basab Kundu is currently working at Arm as System Validation Tech Lead primarily focusing on Emulation platform for validation and simulation acceleration. In the past he had worked with Infineon, AMD, Intel, C-DOT (Center for development of telematics) in different capacities like Hardware board and system development, Embedded software, Analog characterization, co-simulation (CPU, IO hub), Simulation acceleration (emulation), SoC validation/debug, Post-silicon characterization, Pre-silicon methodology development, etc. He has 30 years of industry experience and has bachelor’s degree from IIT Kharagpur.
Vikash Chandra
Director Engineering
SE SoC Engineering
Vikash Chandra is with Arm from past 9+ Years and having overall Industry experience on 21+ years of experience in VLSI ASIC Design, Verification and Implementation. He has worked on IP Unit, Sub-system and SoC level verification and validation involving simulation and emulation-based platform. He has extensively worked on PCIe IP verification in past and currently leading Arm system IP, Compute subsystem , SoC system level verification which also involves using PCIe and CXL as verification component. Vikash completed his B.E in Electronics and Communication in the Year 2001 followed by PG specialization in VLSI design at CDAC Hyderabad.
Deepak Yeggina
Senior Principal Engineer
SE SoC Engineering
Deepak Yeggina is with Arm for the past 18 years. He has been developing tools for functional verification of Processors and System-IP using Random Stimulus generation approach. He holds a Masters in Computer Science from SSSIHL.

Cadence speakers

Name  Profile

Abhay Apte
Senior Principal Application    Engineer                       
Verification – Mixed Signal              

Abhay has 20+ years of experience in EDA mainly on Cadence’s Analog & Mixed signal simulation methodologies. He is currently working as Sr. Principal Application Engineer in the Global Customer Success Team at Cadence.His primary responsibilities include guiding his team towards customer success, product knowledge creation & mentoring.  His main interests are in solving design automation challenges related to AMS simulation methodologies, Design reliability and EMIR (Electromigration & IR).
Amit Kothari
Senior Principal Application Engineer       
Physical Design                      
Amit Kothari has been working for Cadence Design Systems India Pvt. Ltd. since 2006. With Overall 16+ years of Industry experience, he has expertise and interests in the areas of Design For Manufacturing, Physical Verification, Parasitic Extraction and Rule Deck Development for DRC/LVS. He has vast experience as a Sr. Principal Application Engineer focusing on Cadence Physical Verification tool suite, its customers and loves to teach and guide new engineers with Physical Verification Rule writing methodologies. He is a handy trainer and Customer Support professional, currently creating Knowledge artifacts for Cadence DFM/Physical Verification products.
Anil T S
Application Engineer Architect
Verification - Emulation
Anil has over 24 years of experience in HW design, Emulation and Prototyping . Worked with many companies like Mistral, KPIT, Altera(Intel) and Lattice prior joining cadence in 2011. In cadence started with Protium R&D as a WW deployment PE for Protium in 2011 and then moved to field. Now managing the India emulation and Prototyping field team.
Bharat Bhushan
Senior Principal Application Engineer
Physical Design
Bharat has been working with Cadence since 2011 as an application engineer. He has hands on experience on wide range of digital implementation technologies - Synthesis, Place and Route, Timing and power signoff and Parasitic extraction.  As an AE, Bharat has worked with some of the top design houses in industry helping optimize their recipes to squeeze the best PPA. Currently, he leads the AE team working on digital tools [Innovus/Genus/Tempus].
Budi Murty
Senior AE Manager
Verification - Digital
Budi has been working with Cadence since 2006 started as an Application Engineer. He has wide experience on verification technologies along with the Cadence platforms like – Xcelium, vManager and Safety. He has worked in closed collaboration with different customers around the globe to optimize the verification cycle in terms of regression throughput, automation, coverage closure, etc. Currently, he is working as Sr. AE Manager managing AE team working on different Cadence verification tools.
Navdeep Sood
Senior Principal Application Engineer
Design for Test
Navdeep is a highly accomplished professional presently managing DSG DFT team for the Global Customer Success team at Cadence, Noida. With 14 years of extensive experience in the field, he possesses a comprehensive understanding of various aspects of Design-for-Test (DFT) and Test methodologies. His academic background includes an MTech degree from Punjab Engineering College. His research interests focus on cutting-edge areas such as Optimized Test Point using AI &ML,  3D IC, Physical aware DFT, and Hierarchical ATPG. He is actively involved in pushing the boundaries of semiconductor technology and addressing the challenges posed by advanced chip designs. As evidence of his expertise, he has published three papers in renowned IEEE conferences, including the prestigious International Test Conference (ITC-Anaheim). He has successfully trained hundreds of DFT Engineers across various companies on the efficient utilization of Cadence DFT and ATPG EDA Tools.
Sameer Garg
Senior Principal Application Engineer
Physical Design
Sameer has 15 years of experience in semiconductor industry. At present, working as a senior principal support application engineer in Global Customer Success team at Cadence Design Systems Inc. Providing support on Custom IC design EDA tool to worldwide customers. Hands-on experience on the Virtuoso domain products like Virtuoso Schematic Editor, Virtuoso Layout Suite L/XL/GXL/EXL/MXL tiers, Virtuoso Floor planner, Design planning and Analysis, Custom placement and routing solutions. Worked on different advanced nodes from multiple foundries. Expertise in SKILL language programming on Virtuoso platform customization and automation.
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