i am developing on ARMv8 a57 based CPU, i wonder how could i obtaib the bandwidth between L1 cache and L2 cache cause i could not find any related information from a57 techinicial reference manual.
as you know, the STREAM can tell the BW accessing the mem, and the BW between registers and L1 cache can be founfd in the manual.
@icurry, Not sure how this fits under "Infrastructure Solutions". This post has been moved to the "SoC Design"  category as you are referencing the development of an ARMv8 based CPU. This question might also be better positioned in the "Cortex-A / A Portfolio"  category.
: https://community.arm.com/developer/ip-products/system/f/soc-design-forum: https://community.arm.com/developer/ip-products/processors/f/cortex-a-forum
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