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Users of Arm processors can be all over the planet, and now they have a place to come together. The processors community is the place to be all things processor-related.
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Unanswered questions
Clean and invalidate cache ARMV8
Not Answered
5 minutes ago
How To Swap From 32-bit Mode To 64-bit Mode In An Android that has ARMV8-A OS
Not Answered
7 months ago
Which register excactly control the endiness in the EL0 data access? SPSR_EL1 or SCTLR_EL1?
Answered
4 days ago
How to handle Interrupt with certain interrupt ID in Arm Trusted Firmware
Not Answered
3 days ago
Jetson TX2 cortex-a57 crash after enabling mmu
Not Answered
4 days ago
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Clean and invalidate cache ARMV8
0
Cortex-A72
Armv8-A
3
views
0
replies
Started
5 minutes ago
by
Rifakst
Not Answered
How To Swap From 32-bit Mode To 64-bit Mode In An Android that has ARMV8-A OS
0
17639
views
4
replies
Latest
18 hours ago
by
42Bastian Schick
Answered
Which register excactly control the endiness in the EL0 data access? SPSR_EL1 or SCTLR_EL1?
0
AArch64
Armv8-A
AArch32
945
views
2
replies
Latest
2 days ago
by
George_
Not Answered
How to handle Interrupt with certain interrupt ID in Arm Trusted Firmware
0
Arm Trusted Firmware
278
views
0
replies
Started
3 days ago
by
whexy
Not Answered
Jetson TX2 cortex-a57 crash after enabling mmu
0
Memory Management Unit (MMU)
558
views
0
replies
Started
4 days ago
by
josecm
Not Answered
Rowhammer bug on ARM
0
Cortex-A72
Armv8-A
508
views
0
replies
Started
4 days ago
by
Frederick
Not Answered
How can I trigger an SError exception on a cortex A processor
0
ARMv8 Exception Model
Armv8-A
567
views
1
reply
Latest
4 days ago
by
42Bastian Schick
Not Answered
OSv guest encountering EC - "Unknown Reason" sync exception (ESR = 0x2000000) on Raspberry PI 4B host with KVM on
0
Raspberry Pi
Cortex-A72
Emulation & Virtualization
515
views
0
replies
Started
5 days ago
by
Waldek
Answered
Disable Cache L1 et L2 Armv8
0
Cortex-A72
Cache
Armv8-A
1481
views
7
replies
Latest
5 days ago
by
42Bastian Schick
Not Answered
How to disable the branch prediction on armv8
0
Cortex-A72
Armv8-A
Branch Prediction
1220
views
2
replies
Latest
8 days ago
by
vstehle
Not Answered
aarch64 instruction
0
AArch64
SIMD and Vector Processing Instructions
859
views
1
reply
Latest
8 days ago
by
42Bastian Schick
Answered
Cortex-A7 pipeline is non-symmetric, what does this attribute mean?
0
Cortex-A53
Cortex-A15
Cortex-A
Cortex-A7
9199
views
10
replies
Latest
8 days ago
by
Jerome Decamps - 杜尚杰
Not Answered
CortexA53, FreeRTOS and interrupts
0
950
views
1
reply
Latest
9 days ago
by
42Bastian Schick
Not Answered
Reduced Virtual Interrupt Controller RVIC
0
959
views
0
replies
Started
12 days ago
by
david.loosli
Not Answered
Exception type generated upon hardware reset
0
1 (Reset)
Interrupt
1653
views
1
reply
Latest
14 days ago
by
42Bastian Schick
Answered
Debug using gdb debugger, how to get the exception level?
0
Cortex-A53
Debugging
2454
views
8
replies
Latest
15 days ago
by
Boon Khai
Not Answered
Multicontroller communication
0
1944
views
0
replies
Started
21 days ago
by
RUSurya
Not Answered
Is it possible to turn my phone's 64-bit armv8-a (32-bit mode) to 64 bit mode
0
2722
views
1
reply
Latest
26 days ago
by
Raheem
Not Answered
Interrupts not received in secure world for Cortex A7 in Trsuty
0
Arm Trusted Firmware
Cortex-A7
3017
views
1
reply
Latest
28 days ago
by
42Bastian Schick
Not Answered
Why don't we see 8+ Cortex A77 cores in a cheap desktop device? Are there driver issues with Linux for such a device?
0
3551
views
1
reply
Latest
30 days ago
by
Zhifei Yang
>