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Users of Arm processors can be all over the planet, and now they have a place to come together. The processors community is the place to be all things processor-related.
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Unanswered questions
BURST option in AHB-to-AHB sync-up bridge
Not Answered
4 days ago
Why does Arm still support short descriptors?
Suggested Answer
11 hours ago
In Arm v7 mmu, stage2 translation cannot use short descriptors. WHY?
Answered
9 months ago
Processor halt in __libc_init_array assembler function
Answered
9 days ago
Cache Coherence Support in CHI Specification
Not Answered
6 days ago
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BURST option in AHB-to-AHB sync-up bridge
0
2071
views
3
replies
Latest
6 hours ago
by
Hendricks
Suggested Answer
Why does Arm still support short descriptors?
0
Armv7-A
Armv8-A
Memory Management Unit (MMU)
448
views
1
reply
Latest
8 hours ago
by
Andy Neil
Answered
In Arm v7 mmu, stage2 translation cannot use short descriptors. WHY?
+1
EL1
Armv7-A
EL0
Memory Management Unit (MMU)
Hypervisor
5905
views
3
replies
Latest
9 hours ago
by
Martin Weidmann
Answered
Processor halt in __libc_init_array assembler function
0
3225
views
8
replies
Latest
2 days ago
by
Andy Neil
Not Answered
Cache Coherence Support in CHI Specification
0
1841
views
0
replies
Started
6 days ago
by
JO16
Not Answered
making physical memory pages not cacheable (probabaly by modifying page table entry)
0
1641
views
0
replies
Started
6 days ago
by
Gol
Not Answered
Debug Connection Cause ExecutionTiming Problem on Second Core of Cortex A9 on Zynq 702 MPCore
0
System on Chip (SoC)
Cortex-A9
2735
views
3
replies
Latest
6 days ago
by
BurakSeker
Not Answered
flush_cache_all() API consuming 200+ microseconds.
0
2116
views
5
replies
Latest
9 days ago
by
vaiyawa
Not Answered
A35 Power Mode Transitions
0
1448
views
1
reply
Latest
10 days ago
by
42Bastian Schick
Answered
Address memory of the next instruction in A9 MPCore
0
R15 (PC Program Counter)
1983
views
3
replies
Latest
11 days ago
by
dVaquerizo
Answered
How to flush write buffer when memory attribute is normal_nc
0
Cache coherency
2213
views
4
replies
Latest
11 days ago
by
bamvor_china
Suggested Answer
ARM R5 and A53 cores coexist
0
2132
views
2
replies
Latest
12 days ago
by
Stuart Hirons
Not Answered
What can cause getting Cortex-A55 DSU P-Channel PACCEPT/PDENY signals fail?
0
Cortex-A55
Armv8-A
Cortex-A
1552
views
0
replies
Started
12 days ago
by
Emmy0
Not Answered
The "usage model" of ARMv8 SVE contiguous "non-fault" load instructions ?
0
Armv8-A
2909
views
2
replies
Latest
15 days ago
by
alexn
Not Answered
How to do from Secure(EL3) to Non-secure Exception level transition in ARMV8-A ?
+1
EL1
EL3
EL2
AArch64
ARMv8 Exception Model
2891
views
4
replies
Latest
17 days ago
by
Mr_Sanjay
Suggested Answer
Partial register dependency neon
0
Cortex-A57
AArch64
optimization
NEON
6783
views
4
replies
Latest
17 days ago
by
doofenstein
Not Answered
Building Ne10 Library With ArmCompiler 5 on ARM Cortex A9
0
Arm Compiler 6
Cortex-A9
NEON
Arm Compiler 5
1859
views
0
replies
Started
17 days ago
by
BurakSeker
Not Answered
Resetting GIC by SW?
0
Cortex-A53
GICv3/v4
Cortex-M3
1699
views
0
replies
Started
17 days ago
by
kabel
Not Answered
[ArmV8] [Cortex-A53] [PMU] PM_CCNTR to measure cpuload
0
Cortex-A53
performance analysis
Armv8-A
1704
views
2
replies
Latest
18 days ago
by
Amr Fawzy
Answered
how to return from exception generated by SMC instruction
0
Cortex-A53
EL1
EL3
EL2
AArch64
Armv8-A
Cortex-A
5560
views
4
replies
Latest
24 days ago
by
T6yson
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