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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3586 Questions
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  • Not Answered

    Forum FAQs 0

    • ARM Community
    8507 views
    0 replies
    Started over 4 years ago
    by Annie
  • Answered

    Correctly invalidating Cortex-A53 shared L2 cache for access through ACP? +1

    • Cortex-A53
    • Cache coherency
    • AXI4
    • Cache Management
    • Cache Architecture
    146 views
    2 replies
    Latest 19 hours ago
    by Dylan Barrie
  • Suggested Answer

    clarifications about ARCACHE bits in AXI4 0

    284 views
    2 replies
    Latest 1 day ago
    by Srilakshmi beeram
  • Not Answered

    Number of outstanding transactions in AXI 0

    • performance
    • AXI4
    • interconnect
    51 views
    0 replies
    Started 2 days ago
    by alinx
  • Answered

    Shift right instruction 0

    • AArch64
    297 views
    2 replies
    Latest 3 days ago
    by Eduard Kachalov
  • Not Answered

    How to implement divide with MVE intrinsic (Cortex M85) 0

    • Helium
    • MVE Intrinsics
    • Armv8.1-M
    115 views
    1 reply
    Latest 3 days ago
    by fjpmbb
  • Suggested Answer

    The behaviour of writenosnp and readnosnp that require request order in CHI 0

    258 views
    1 reply
    Latest 9 days ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    axi ID problem 0

    173 views
    1 reply
    Latest 9 days ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    what is difference between read unique and clean unique? 0

    167 views
    1 reply
    Latest 9 days ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    Setting up cache coherent transactions using CCI-500 0

    • Cortex-A72
    • Cache coherency
    • ACE
    • ACE-Lite
    • CoreLink CCI-500 Cache Coherent Interconnect
    187 views
    1 reply
    Latest 9 days ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    retry problem 0

    • AMBA 5 CHI
    155 views
    1 reply
    Latest 9 days ago
    by Christopher Tory Arm Employee Badge
  • Not Answered

    Dynamic Core Management via Arm's PSCI on OdroidC4 0

    • Kernel Developers
    • smp
    • ODroid
    • cpu
    • psci
    • Software Development
    120 views
    0 replies
    Started 12 days ago
    by Michael Mospan
  • Suggested Answer

    timing diagram 0

    • AMBA 5 CHI
    278 views
    3 replies
    Latest 14 days ago
    by Ben Hicks Arm Employee Badge
  • Answered

    DMA Controller PL230 - Representation of PL230_DMA_CHNL_BITS 0

    • Architecture
    • DMA Devices
    • PrimeCell µDMAController (PL230)
    267 views
    2 replies
    Latest 21 days ago
    by Oliver Beirne Arm Employee Badge
  • Answered

    How to Modify RME Register Values and the LEGACYTZEN Signal on ARM V3AE CPU 0

    • Security
    • Development Boards
    186 views
    1 reply
    Latest 22 days ago
    by Peter Harris Arm Employee Badge
  • Answered

    Enabling Arm CCA on Nvidia Jetson AGX Thor with Neoverse-V3AE CPU +1

    382 views
    1 reply
    Latest 24 days ago
    by Peter Harris Arm Employee Badge
  • Answered

    Race Conditions in CXS interface protocol. Why? +1

    • CXS
    • Interface Bus Architecture
    174 views
    1 reply
    Latest 27 days ago
    by Oliver Beirne Arm Employee Badge
  • Not Answered

    Race Conditions in CXS interface protocol. Why? 0

    • CXS
    • Interface Bus Architecture
    147 views
    0 replies
    Started 27 days ago
    by SY FPGA
  • Suggested Answer

    CPAKs: Cycle accurate simulator/emulator for a Cortex M4 processor based board 0

    • Cycle Performance Analysis Kits
    • Cortex-M4
    233 views
    2 replies
    Latest 27 days ago
    by Mustapha Ghliss
  • Not Answered

    Enabling CCA on NVIDIA Jetson AGX Thor with Neoverse-V3AE CPU​ 0

    • Neoverse V3
    • Security
    168 views
    0 replies
    Started 1 month ago
    by Junjie Huang
>
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