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Users of Arm processors can be all over the planet, and now they have a place to come together. The processors community is the place to be all things processor-related.
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Unanswered questions
Can I run an A9 program under A53 without any modification
Not Answered
1 hour ago
Reading ETB from software
Not Answered
6 days ago
Does Qualcomm Centriq 2400 support sve instruction set?
Suggested Answer
12 days ago
Why aarch64 and x86 not support conditional execution like before?
Not Answered
11 days ago
System Frequency for CortexA35
Answered
14 days ago
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Not Answered
Can I run an A9 program under A53 without any modification
0
57
views
0
replies
Started
1 hour ago
by
wangdasheng
Not Answered
Reading ETB from software
0
CoreSight ETB11
Cortex-A9
1783
views
1
reply
Latest
6 days ago
by
42Bastian Schick
Suggested Answer
Does Qualcomm Centriq 2400 support sve instruction set?
0
2749
views
5
replies
Latest
10 days ago
by
42Bastian Schick
Not Answered
Why aarch64 and x86 not support conditional execution like before?
0
1830
views
1
reply
Latest
11 days ago
by
42Bastian Schick
Answered
System Frequency for CortexA35
0
Cortex-A35
Armv8-A
2496
views
1
reply
Latest
13 days ago
by
vstehle
Answered
mips of cortex a53
0
4216
views
6
replies
Latest
14 days ago
by
vstehle
Not Answered
PMU's cycles counter showing unstable values
0
4610
views
8
replies
Latest
15 days ago
by
Zhifei Yang
Answered
can we delay read and write transactions(axi4) by providing delay in register slice?
0
AXI4
54629
views
66
replies
Latest
19 days ago
by
Wilson7E
Not Answered
can i get cpu run state aarch64 or aarch32 fo cortex a57?
0
5022
views
3
replies
Latest
19 days ago
by
jhb
Not Answered
Raspberry pi with ARMV8.2 support
0
Raspberry Pi
4523
views
1
reply
Latest
22 days ago
by
42Bastian Schick
Not Answered
which library should be used for half-precision mathematic functions?
0
4961
views
8
replies
Latest
23 days ago
by
42Bastian Schick
Answered
Setting PC for and waking up secondary cores from the primary core
+1
Armv8-A
10292
views
12
replies
Latest
29 days ago
by
jhoney
Answered
Memory corruption in mov R4, 0; add R1, SP, #16; STB R4,[R1,#-1]! on Cortex-A9 with cache enabled, many interrupts EMAC, Timers after hours run. Not seeing in errata. R1 is not decremented and results corrupted stack data abort. Debugger not factor.
+1
7216
views
5
replies
Latest
1 month ago
by
timholt
Answered
What are the necessary preconditions to load a guest into EL1 from EL2?
+1
EL1
EL2
ARMv8 Exception Model
Armv8-A
Hypervisor
6219
views
2
replies
Latest
1 month ago
by
MarekBykowski
Not Answered
Cortex-A35 CoreMark results
0
4942
views
0
replies
Started
1 month ago
by
Etienne Alepins
Answered
Atomic write (LDAXR/STLXR) causes infinite loop on Cortex-A72
+1
Cortex-A72
AArch64
5214
views
1
reply
Latest
1 month ago
by
42Bastian Schick
Answered
Cortex A9 core locks and cant't stop it
+1
Debug Tools and Test Methods
8050
views
1
reply
Latest
1 month ago
by
42Bastian Schick
Answered
How to set secondary core's registers from primary arm?
0
Cortex-A15
Cortex-A
14422
views
12
replies
Latest
1 month ago
by
42Bastian Schick
Answered
Difference between ARMv8 Data Abort exception subtypes "Not in translation table" and "Translation table fault at level"?
+1
AArch64
Armv8-A
System MMU
7296
views
2
replies
Latest
1 month ago
by
Branden Sherrell
Suggested Answer
Emissivity value A72
0
7587
views
1
reply
Latest
1 month ago
by
Christopher Tory
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