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Description
Users of Arm processors can be all over the planet, and now they have a place to come together. The processors community is the place to be all things processor-related.
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1308 Questions
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Forum FAQs
5 months ago
Would and How arm/trustfirmware take care of cache coherence in trustzone technology?
Answered
10 months ago
Differences between Armv7 to Armv8?
Answered
over 7 years ago
Bare Metal Code Development for iMX8M Mini
Not Answered
3 days ago
cortex a53 : How to detect cached data is invalid ? (use ddr memory)
Answered
15 days ago
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0
ARM Community
6477
views
0
replies
Started
5 months ago
by
Annie
Answered
Would and How arm/trustfirmware take care of cache coherence in trustzone technology?
0
10394
views
2
replies
Latest
7 hours ago
by
zilly
Answered
Differences between Armv7 to Armv8?
0
112228
views
9
replies
Latest
8 hours ago
by
Pittsburgh Services
Not Answered
Bare Metal Code Development for iMX8M Mini
0
Arm Compiler
Compilers
Baremetal
414
views
13
replies
Latest
19 hours ago
by
42Bastian Schick
Answered
cortex a53 : How to detect cached data is invalid ? (use ddr memory)
0
Cache Controllers
Cache Management
814
views
5
replies
Latest
1 day ago
by
Nickpalmer
Not Answered
Why performance is higher on LITTLE cores?
0
big.LITTLE
performance
multithreading
1303
views
14
replies
Latest
2 days ago
by
zois
Not Answered
ACE protocol Acknowledgement signal
0
48
views
0
replies
Started
2 days ago
by
ash11
Not Answered
ACE protocol barrier and dvm transactions
0
45
views
0
replies
Started
2 days ago
by
ash11
Not Answered
AXI slave design and verification
0
408
views
6
replies
Latest
4 days ago
by
ash11
Not Answered
ACE protocol cache state
0
76
views
0
replies
Started
6 days ago
by
ash11
Not Answered
partial cache line store in ACE
0
67
views
0
replies
Started
9 days ago
by
ash11
Not Answered
Transactions sequencing by interconnect in ACE protocol
0
79
views
0
replies
Started
15 days ago
by
ash11
Answered
some question about ACE
0
ACE
290
views
3
replies
Latest
15 days ago
by
vstehle
Not Answered
Bare metal startup code for Cortex-78 CPUs
0
447
views
6
replies
Latest
19 days ago
by
Zenon Xiu (修志龙）
Answered
Taking exceptions from EL1 to EL1: Problems with SVC
0
Cortex-A53
AArch64
ARMv8 Exception Model
1499
views
12
replies
Latest
22 days ago
by
Zenon Xiu (修志龙）
Answered
SMMU: Why do the software in EL1 can modify the TTB of S2 in stream table entry when stage 2 is enabled?
0
501
views
6
replies
Latest
23 days ago
by
林军
Not Answered
Cortex-A15MP Core Registers
0
23954
views
8
replies
Latest
23 days ago
by
Sheila
Not Answered
Difference between SP_EL1 and SPSEL + MOV
0
892
views
6
replies
Latest
23 days ago
by
42Bastian Schick
Not Answered
physical and virtual timer.
0
281
views
2
replies
Latest
25 days ago
by
Zenon Xiu (修志龙）
Answered
Virtual interrupt EOI mode & irq state
0
GICv2
GICv3/v4
virtualization
1242
views
3
replies
Latest
28 days ago
by
HenryW1991
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