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ARM Cortex ICode, DCode, System buses

Felix Varghese
Note: This was originally posted on 26th February 2009 at http://forums.arm.com

I'm a bit confused about the bus structure and memory model of ARM Cortex M3. First of all, does Cortex M3 actually have 3 physically separate buses coming out of it?
They say that an instruction fetch in the code memory is over the ICode bus and data fetch is over DCode bus. So if i have some flash memory mapped into code memory region, which is used to store my code and some constant data, then how exactly would i connect the two buses to it? Would i connect two Code buses to the same physical IC?
And if i have a RAM chip mapped to the SRAM memory region used to hold my normal data, would i connect the system bus to it so i can perform normal data fetches over it?
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    Note: This was originally posted on 26th February 2009 at http://forums.arm.com

    Thanks a lot folks.. The picture is getting clearer.. but here when we say ICode bus or DCode bus or just 'bus', does it mean the address bus (whatever carries the fetch or write address) and data bus (whatever carries the data being fetched or written) together or just the data bus ?
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    Note: This was originally posted on 27th February 2009 at http://forums.arm.com

    Thanks again guys for all your attention :) Okay, so does it also mean that if i connect ICode and DCode interfaces to separate physical memory chips then i'll be able to use Cortex M3 like a true Harvard machine with the same address meaning different places for instruction and data operations? Like good old 8051 ??
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    Note: This was originally posted on 2nd March 2009 at http://forums.arm.com

    Yes i get your point.

    Just in case we are talking about different things -

    Are you thinking about taking an off-the-shelf Cortex-M3 microcontroller and adding physical memory devices to it, or actually designing and building a Cortex-M3-based microcontrooler SoC design?

    Cheers,

    Iso



    No i'm not actually into hardware design.. I just wanted to know how it is done [:)]
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    Page 31 of the Cortex-M3 technical reference manual has quite a comprehensive diagram of the internal and external bus interconnect of Cortex-M3, and illustrates that it has four physical busses coming out of it.

    As can be seen on page 90, the external APB uses addresses 0xE0040000-to-0xE00FFFFF, the System bus uses 0x20000000-to-0xDFFFFFFF and 0xE0100000-to-0xFFFFFFFF. The D-Code and I-Code buses however, share the address range 0x00000000-to-0x1FFFFFFF.

    Cortex-M3 assumes that a read to the same address on either the D-Code or I-Code ports will access the same data; how this is achieved is up to the implementor, but can make a significant difference to the performance of the device, options (not necessarily all practical) might include:

    1. Simple arbiter (matrix) into a single slave (Flash/ROM/RAM).
    2. Flash with prefetching to I-Code and a bypass for D-Code.
    3. Dual-port RAM with read-only to I-Code, and read/write to D-Code.
    4. Some kind of cache system - possibly supporting hit-under-miss between I/D-Code.

    Currently available Cortex-M3 microcontrollers today typically have a flash-controller at 0x00000000+, with SRAM and peripherals on the System-bus at 0x20000000+.

    hth
    s.
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    Note: This was originally posted on 26th February 2009 at http://forums.arm.com

    A bus matrix typically has multiple masters and multiple slaves connect to it, and it will arbitrate between them to make sure that everyone can talk without data loss or corruption.

    So basically you plug both the I and D Cortex-M3 master ports in the same bus matrix, and the RAM and Flash slave ports in to the same matrix, and I-side and D-side accesses can access both memory types.

    Some systems may include dedicated bus-matricies and slave memories on each interface for performance reasons, but this is unusual in "generic" designs.
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    Note: This was originally posted on 26th February 2009 at http://forums.arm.com

    Both the I and D bus interfaces have to carry address information (where to read/write the data or read the instruction from) and send / receive some payload (instruction or data). So both I and D master ports will have an "address bus" and a "data bus".

    The only difference is that the IBus master can only ever issue read transactions (I-side can never write data) so the extra logic to handle writing data from the master port is optimized away to save power and area.
  • 0
    Note: This was originally posted on 27th February 2009 at http://forums.arm.com

    Yes, but...

    As far as I am aware all ARM tools make use of literal pools which are read-only data sections packed inline with the instruction stream - so you need small fragments of the instruction ROM region to be accessible from the D-side memory port.

    This is normally accomplished by having a memory device which is accessible by I and D masters, and then potentially a separate RAM for data which is only accessible from the D master. The bus arbitration inside the matrix makes this as efficient as possible.

    So, while possible, having 100% separate memories for I and D-sides is not normally useful with off the shelf tools such as ARM RVCT or GNU GCC.
  • 0
    Note: This was originally posted on 27th February 2009 at http://forums.arm.com

    Just in case we are talking about different things -

    Are you thinking about taking an off-the-shelf Cortex-M3 microcontroller and adding physical memory devices to it, or actually designing and building a Cortex-M3-based microcontrooler SoC design?

    Cheers,

    Iso