State Machine for AHB-Lite Protocol

This is more of a conceptual doubt than a doubt in protocol. I've come across many papers where state machines are designed for AHB and AHB-Lite. I never understood why a state machine is required and where exactly is it incorporated(inside the processor or in the master interface?).

Also, during any point of time, there will be two transfers in two different states (address phase of current transfer coincides with data phase of previous transfer). So will there also be two different state machines deployed at any moment?

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