I am working on design of APB master and slave connected back to back. Slave component has simple reg with 16 locations
As per APB, for READ/WRITE transaction from master I am generating PSEL = 1 in the first clock cycle and then PENABLE = 1 in the next clock cycle.
During the two clock cycles, PADDR, PWDATA, PWRITE signals does not change. Here APB slave drives PREADY always HIGH. So the PENABLE goes to '0' in the second clock cycle as per the protocol.
Question here is when should APB slave SAMPLE the Control/Data Signals from Master for both READ/WRITE transfers ? Is it in the SETUP phase or the ACCESS phase.
We need to drive the PREADY and PSLVERR and the PRDATA from slave at the same clock for the read transfer (which should happen in the ACCESS phase here).
Hope my query is clear here. Please share inputs.
I think in my first reply I said "Control signals should be sampled by the peripheral at the end of the setup phase", so this would then allow the peripheral to start driving PRDATA at the start of the access phase, and so allow the transfer to complete at the end of a single cycle access phase if the peripheral's access time allows PRDATA to be valid at the end of that cycle.
This is how read accesses can be completed in 2 cycles, and is how accesses HAD TO work in the first releases of APB where there was no PREADY signal.