We need a clarification on Read Data Interleaving on AXI4
Read Data Interleaving is supported in AXI4 and following is my understanding on Data Interleaving:
Multiple Read commands can be executed simultaneously and data interleaving is supported as long as all condition for ordering are followed.
I think data interleaving should not be done within a single burst. In other words, any single burst should contain data from single read command and no burst should contain data from multiple command.
I tried to confirm it but could not find a reference for it.
Can anyone confirm it or point me to a reference document for confirmation.
>Multiple Read commands can be executed simultaneously and data interleaving is
>supported as long as all condition for ordering are followed.
Yes, your understanding is correct.
Read data interleaving can be considered as:
- RDATA for different IDs can be returned out of order.
- RDATA for different IDs can be returned in an interleaved way.
- RDATA for the same ID must be returned in the same order as the AR commands.
Suppose the master has issued two AR commands:
AR1: INCR4, ID=x
AR2: INCR4, ID=y
In this case, since the two commands have different IDs, the RDATA beats (4 beats for each command, 8 in total) can come back completely out of order and interleaved. In other words, on each cycle, either RDATA(ID=x) or RDATA(ID=y) may be returned, and the master must be able to accept them.
Thanks for the reply but I still have some concern on last line of your reply.
Let me get a reconfirmation on mixing of two bursts.
There are two two read transactions issued by Master X and Y, each with 4 beat of single burst.
I agree to your point of X and Y can start in any order, but what I thought is that
Once and of the transaction start, it will complete before other transaction can begin. As both the transactions are of single burst.
It can be
Seq 1: X1 X2 X3 X4 Y1 Y2 Y3 Y4
Seq 2: Y1 Y2 Y3 Y4 X1 X2 X3 X4
Seq 3: X1 Y1 X2 Y2 X3 X4 Y3 Y4
Where X1 and Y1 represents one beat of a single burst.
If you are suggesting that data can come in Seq 3, can you please point me to a reference for that.
>Seq 1: X1 X2 X3 X4 Y1 Y2 Y3 Y4
>Seq 2: Y1 Y2 Y3 Y4 X1 X2 X3 X4
>Seq 3: X1 Y1 X2 Y2 X3 X4 Y3 Y4
>Where X1 and Y1 represents one beat of a single burst.
>If you are suggesting that data can come in Seq 3, can you please point me to a reference for that.
Seq 3 is possible.
Confirmation can be found in the AXI/ACE specification (ARM IHI 0022E):
Data from read transactions with different ARID values can arrive in any order. Read
data of transactions with different ARID values can be interleaved.
<<ARM IHI 0022E>> is available at:
ARM Information Center
--> AMBA specifications
--> AMBA AXI and ACE specification
--> Issue E
You may need to register as an ARM user before downloading.
Thanks for the reference, but I have already gone through that earlier. Though it does say that data can arrive in any order but it does not clarify if it can be mixed in a single burst.
Earlier I have serched the web to find a reference. I dint find anything to confirm my claim of Data interleaving from two data burst is not possible however, I did find it for write transaction (not for read which I was looking for).
I thought same should be applicable for read also, until unless it documented somewhere, that data interleaving for different burst in read transaction is allowed.
As you will be knowing, Write data interleaving support is discontinued from AXI-4, The link is just for reference.
Hopefully the picture below can illustrate the permitted read data behavior.
There are two AR transactions with different IDs. The RDATA in this example is both out of order and interleaved. It is just a mixture of the following two statements from the spec:
Data from read transactions with different ARID values can arrive in any order.
Read data of transactions with different ARID values can be interleaved.
Regarding write data interleaving, the requirements are different from those for read data.
AXI3: Write data interleaving (for different IDs) is supported. But the first item of write data must be issued in the same order as the write address.
AXI4: Write data interleaving is not supported.
Although write data interleaving is allowed in AXI3, masters developed by ARM (such as Cortex-R4) do not generate interleaved write data.
Thanks for all your time and effort. I don't find anything wrong in accepting your views and most likely you are correct. But I think it should be gratified, different people understand things differently. Its just two different way of looking at same thing. As you are and Employee, I would take your views but please ask someone to document it. Again thanks a lot.
this is what written in the spec: "AMBA® AXI Protocol, Version: 2.0" pg 8-6
>>However, a master interface can interleave write data with different WID values if the slave interface has a write data>> interleaving depth greater than one.
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