Setting MPU_RASR for Memory Protection Unit with correct values of TEX/C/B/S bits


I use LPC4078 with an Cortex-M4 core and would like to implement Memory Protection Unit (MPU). Therefore I need to set TEX/C/B/S bits in RASR register but unfortunately am not sure what would be the correct values. In Cortex-M4-User-Guide I only find this table:

I want to protect bootloader area in ROM memory space 0x0000 - 0x8000 (32k) from beeing erased or written. I would assume the following values:

SIZE=14 (32k)
SRD=0 (complete bootloader region active)
B=0 (not bufferable because it's ROM?)
C=1 (cacheable yes or no?)
S=1 (not shareable yes or no?)
TEX=0 (??? What would be normal here?)
AP=3 (Read only, by privileged or unprivileged software because I only want to prevent erasing and writing to bootloader area)
XN=0 (instruction fetches enabled?)

What about these values?



  • Hi Daniel,

    Assuming that you want to program one of the MPU region to your bootloader ROM memory address, you can consider programming to below values with the reason listed adjacent to it.

    ENABLE = 1:

    - Yes, this bit need to be set to 1 so that this MPU region gets enabled when the MPU is enabled


    - Depending on your application, you can choose to program your SIZE in bytes.  Note that the minimum size is 32 bytes.

    SRD = 0:

    As I understand, since you do not want to divide the MPU region to multiple sub-regions, setting this bit to zero makes sense.

    TEX, S, C, B:

    It is important to understand that all of the above bits are considered together in order to identify a particular attribute of a memory region. If it is Boot ROM, then in general, it is considered to be a Strongly-ordered sharable memory in which case you can choose the settings of TEX C B to be all zeros. However, if Boot ROM is considered to be a non-sharable device memory, then TEXCB need to be programmed as  5'b01000.


    Considering your requirement is to make the access as only Read-only by both privileged and unprivileged software, you need to program AP = 3'b111.


    Yes, since boot ROM may contain vector table address, in general, it is necessary to have instruction fetch enabled in which case, it will be zero only. If XN is set to 1, then instruction fetches are not allowed.

    Hope this helps.



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