• State Accepted Answer
  • Locked Locked
  • Replies 8 replies
  • Subscribers 348 subscribers
  • Views 10059 views
  • Users 0 members are here
Options
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Unaligned accesses - CMSDK Example Cortex M0

eugch

The spec mentions that the M0 will generate a Hardfault when unaligned accesses are detected. I would like to find out where is this implemented in RTL and understand it a little better.

Does the GCC compiler detects unaligned code accesses during compilation as well?

Parents
  • 0 in reply to eugch
    eugch said:
    Code accesses as I understand it now is expected to the word aligned and internally the MCU has hardware to detect unaligned code accesses and issue a hard fault.

    There are 4 byte and 2 byte instructions. Each can be on a 4 or 2 byte address. There is no way to have a PC with an odd address or more precisely the least significant bit is ignored (it is the Thumb-2 indication, which is not needed on a Cortex-M which is Thumb-2 only!).


Reply
  • 0 in reply to eugch
    eugch said:
    Code accesses as I understand it now is expected to the word aligned and internally the MCU has hardware to detect unaligned code accesses and issue a hard fault.

    There are 4 byte and 2 byte instructions. Each can be on a 4 or 2 byte address. There is no way to have a PC with an odd address or more precisely the least significant bit is ignored (it is the Thumb-2 indication, which is not needed on a Cortex-M which is Thumb-2 only!).


Children
No data