Unaligned accesses - CMSDK Example Cortex M0

The spec mentions that the M0 will generate a Hardfault when unaligned accesses are detected. I would like to find out where is this implemented in RTL and understand it a little better.

Does the GCC compiler detects unaligned code accesses during compilation as well?

Parents
  • As I understand it the instruction fetch hardware does this.  That is an assembly instruction word needs to be aligned to 4 bytes.  For example first instruction at address 0x1000 and then second one at 0x1004, etc.  What happens is if you have situation where you jump to a bad address, branch to 0x1002 as an example. 0x1002 is not word aligned and hence a hard fault occurs. 

    These hard faults are common when you have stack overflows, or buffer overflows in your code.  They can also happen when you dereference a function to pointer which has not been set correctly.  

    Thus the compile generates code that is word aligned during compile, but the dynamic aspects of the code can cause the error. 

Reply
  • As I understand it the instruction fetch hardware does this.  That is an assembly instruction word needs to be aligned to 4 bytes.  For example first instruction at address 0x1000 and then second one at 0x1004, etc.  What happens is if you have situation where you jump to a bad address, branch to 0x1002 as an example. 0x1002 is not word aligned and hence a hard fault occurs. 

    These hard faults are common when you have stack overflows, or buffer overflows in your code.  They can also happen when you dereference a function to pointer which has not been set correctly.  

    Thus the compile generates code that is word aligned during compile, but the dynamic aspects of the code can cause the error. 

Children
More questions in this forum