Logic IP, such as Standard Cell (SC) libraries, are the foundation for the entire backend design and optimization flow in modern application-specific integrated circuit designs. Arm has long been building high-quality logic IP, such as SC libraries, with well-established optimization flows. This release offers complete, “bleeding edge” Arm logic IP including both front-end and back-end views, which are 1 or 2 generations newer than the logic IP freely available on DesignStart. This means that, together with Arm processor IP, academic researchers will be able to explore logic IP design and optimization techniques on the latest process nodes
At the 7nm technology node and beyond, logic IP design and optimization is becoming increasingly difficult due to extremely complex design constraints. These include discrete transistor sizing, complicated design rules from semiconductor manufacturers, and increasingly reduced cell-heights for modern standard cell architectures, which further complicate the block-level design technology co-optimization on electromigration, power noise, thermal effects, and routability.
Despite the renowned manufacturing and design challenges aforementioned, few comprehensive studies have been performed for SC design and optimization methodology at the 7nm node and beyond. Recent design technology co-optimization (DTCO) studies focus on a small set of SCs and basic block-level place-and-route studies to explore the impact of manufacturing design rules and SC architectures. However, very few SC design and optimization techniques are discussed for complex combinational logic or sequential cells. More importantly, none of them are publicly available, which prevents academic researchers from being able to understand and explore the implications of semiconductor manufacturing on logic IP design and optimization.
To bridge this gap, we have developed and released a set of design and optimization techniques to generate high-quality and academically available SC libraries for the ASAP7 predictive process design kit.The key techniques include optimized transistor sizing for critical path speedup, transistor placement with generalized Euler paths and back-end design prototyping for library-level explorations. Please note, we are releasing Arm-designed standard cell libraries (7.5-track and 9-track) based on the ASAP7 PDK, which are independent from those listed in the ASAP7 PDK website.
Access the ASAP7 Standard Cell Library
We have built and tested all front-end and back-end views with a full back-end design flow, and all standard cell views have been made freely available for academic usage through Arm DesignStart. In the future, we anticipate a much broader academic impact, while leveraging very recent research on SC library evaluation and optimization, automatic SC synthesis, SC-driven place-and-route towards a full synthesis research flow. If you'd like to access the Arm-designed standard cell libraries, please contact the DesignStart University Licensing team.
Contact the DesignStart Team
This work was presented as an invited paper at the International Conference on Computer-Aided Design (ICCAD) 2017, where we discussed how academic researchers could use our ASAP7 SC library to perform meaningful research on Arm IP. For example, academics may choose to explore transistor sizing and placement, such as how to avoid brute-force efforts for transistor sizing or how transistors can be placed and routed across multiple rows. It is also possible to look at how far track height can be reduced, as well as other, more broad research topics. See the full invited paper or the slides presented at ICCAD 2017 for more detail.
Read the full paper Download the talk slides