Today ARM announced a lower cost, very high performance debug and trace unit to complement the existing ARM DSTREAM and Keil ULINK product families. The ARM DSTREAM-ST unit retains the existing remote network and USB host connection capabilities of its high-end sibling, ARM DSTREAM, but use of a cost-optimized ARM-based hardware platform enables efficient debug of complex SoCs for use cases that do not require high-bandwidth program or instruction tracing.
Figure 1: DSTREAM-ST connected to target board
DSTREAM-ST is a target access/control unit that knows how to communicate with and control ARM cores and ARM CoreSight devices in ARM based SoCs. Most ARM-based SoCs provide JTAG or Serial Wire Debug (SWD) ports through which DSTREAM-ST is able to control the ARM cores for debug purposes. One main use of a DSTREAM-ST unit is in-conjunction with an ARM capable debug tool - such as the ARM DS-5 Development Studio product. For example, when the debugger wishes to read some memory it can send a message to DSTREAM-ST asking it to read memory and the DSTREAM-ST box takes that request and turns it into the complicated set of operations required to interact with the target system to access the requested memory - and DSTREAM-ST has built in knowledge of how to do this for all ARM cores and CoreSight devices.
Another main use for DSTREAM-ST is to collect the large quantities of trace data generated by a target platform and to make this data available to DS-5 so that a user can view the history of target behavior up to the present moment. In fact it is this trace capability which is the main differentiator between the existing DSTREAM and the lower cost DSTREAM-ST.
So let’s take a closer look at DSTREAM-ST and see what it has to offer.
DSTREAM-ST retains the overall sleek look of the DSTREAM product line but uses a refreshed case design to allow more efficient and silent cooling. DSTREAM-ST also does not require the use of a separate probe for target connection, making it more desk space friendly. Host connectivity has been upgraded to support both Gigabit Ethernet and USB3 Super Speed connection. This is important for DSTREAM-ST because unlike DSTREAM, it does not contain any trace RAM into which it can store the collected trace data. Instead, DSTREAM-ST streams all trace data to the host computer over the updated high speed links.
DSTREAM-ST is not positioned as an instruction trace collection device for a complex multi-core SoC. Instead, DSTREAM-ST is positioned at providing debug capability for that complex SoC whilst also supporting the collection of system trace data - such as the data generated by instrumenting code using printf style output - re-targeted to transport over a 4 bit trace port. For such use cases, a 4 bit trace port width is usually sufficient and the streaming of the data to the host is unlikely to be an issue.
DSTREAM-ST supports direct connect to target systems which use the ARM JTAG 20 (debug only), CoreSight 10 (debug only) or CoreSight 20 (debug and trace) connectors. DSTREAM-ST comes supplied with adapters for connection into target systems which use the TI JTAG 14 (debug only) or Mictor 38 (debug and trace) connectors. DSTREAM-ST also supports the use of Serial Wire Debug (SWD) and Serial Wire Output (SWO) for those target systems that support it.
When DSTREAM-ST is used in-conjunction with ARM DS-5 Development Studio both the debugger and Streamline can utilize the streaming trace capabilities. The debugger provides an Events View which is used to view the output from instrumentation trace. For a CoreSight-based system, instrumentation trace means the trace data generated by the System Trace Macrocell (STM) or the Instrumentation Trace Macrocell (ITM). Prior to the availability of DSTREAM-ST, the Events view would wait for the target system to be halted before displaying the printf style data. Now, using DSTREAM-ST streaming trace, the view can display the output data live, so it appears more like a regular output console rather than a trace view.
Streamline, the DS-5 performance analyzer, can utilize the STM data channels during collection of performance data in bare metal type systems. Using DSTREAM-ST, the performance data is live streamed to the host where it is collected and transformed into input data for Streamline to display and analyze.
Figure 2: Streamline Performance Analyzer showing L2 Cache activity
You can of course make use of DSTREAM-ST (and DSTREAM) outside of the DS-5 IDE. ARM provides the RDDI API header files and libraries for you to write your own JTAG applications which use DSTREAM-ST as the target connection. If JTAG is too low level for you, the RDDI APIs also allow access to the built-in device support that DSTREAM-ST provides for the ARM cores, CoreSight devices as well as the trace transport APIs. This opens up DSTREAM-ST for use in production test, production flash programming and regression test systems. Further, you get to choose whether you wish to write your applications in C/C++, Java or Python.If your target device contains some custom or non-ARM IP, the DSTREAM-ST development kit (available separately) can support accelerated access to that device, opening up the possibility of custom device control from within DS-5 or your own applications.
So how do you decide whether to use the existing DSTREAM product or the new DSTREAM-ST product? It’s a pretty simple choice; if you need external instruction trace support for Cortex-A or Cortex-R class cores, or you need local trace storage near your target (DSTREAM has 4GB of local storage), then select DSTREAM. However if you don't make use of external trace, or your use of it is limited to instrumentation trace (or Cortex-M class instruction trace), then DSTREAM-ST may well be a more cost effective option.
For more details on DSTREAM-ST, or any of the other members of the DSTREAM/ULINK family, please check out the product pages on developer.arm.com or contact your local supplier.
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