Welcome to the Arm Neon programming quick reference.
This article aims to introduce Arm Neon technology. Hope that beginners can get started with Neon programming quickly after reading the article. The article will also inform users which documents can be consulted if more detailed information is needed.
This section describes the Neon technology and supplies some background knowledge.
Neon technology is an advanced SIMD (Single Instruction, Multiple Data) architecture for the Arm Cortex-A series processors. It can accelerate multimedia and signal processing algorithms such as video encoder/decoder, 2D/3D graphics, gaming, audio and speech processing, image processing, telephony, and sound.
Neon instructions perform "Packed SIMD" processing:
Neon provides:
Armv8-A is a fundamental change to the Arm architecture. It supports the 64-bit Execution state called “AArch64”, and a new 64-bit instruction set “A64”. To provide compatibility with the Armv7-A (32-bit architecture) instruction set, a 32-bit variant of Armv8-A “AArch32” is provided. Most of existing Armv7-A code can be run in the AArch32 execution state of Armv8-A.
This section compares the Neon-related features of both the Armv7-A and Armv8-A architectures. In addition, general purpose Arm registers and Arm instructions, which are used often for Neon programming, will also be mentioned. However, the focus is still on the Neon technology.
Armv7-A and AArch32 have the same general purpose Arm registers – 16 x 32-bit general purpose Arm registers (R0-R15).
Armv7-A and AArch32 have 32 x 64-bit Neon registers (D0-D31). These registers can also be viewed as 16x128-bit registers (Q0-Q15). Each of the Q0-Q15 registers maps to a pair of D registers, as shown in the following figure.
AArch64 by comparison, has 31 x 64-bit general purpose Arm registers and 1 special register having different names, depending on the context in which it is used. These registers can be viewed as either 31 x 64-bit registers (X0-X30) or as 31 x 32-bit registers (W0-W30).
AArch64 has 32 x 128-bit Neon registers (V0-V31). These registers can also be viewed as 32-bit Sn registers or 64-bit Dn registers.
The following figure illustrates the relationship between Armv7-A, Armv8-A AArch32 and Armv8-A AArch64 instruction set.
The Armv8-A AArch32 instruction set consists of A32 (Arm instruction set, a 32-bit fixed length instruction set) and T32 (Thumb instruction set, a 16-bit fixed length instruction set; Thumb2 instruction set, 16 or 32-bit length instruction set). It is a superset of the Armv7-A instruction set, so that it retains the backwards compatibility necessary to run existing software. There are some additions to A32 and T32 to maintain alignment with the A64 instruction set, including Neon division, and the Cryptographic Extension instructions. Neon double precision floating point (IEEE compliance) is also supported.
This section describes the changes to the Neon instruction syntax.
All mnemonics for Armv7-A/AAArch32 Neon instructions (as with VFP) begin with the letter “V”. Instructions are generally able to operate on different data types, with this being specified in the instruction encoding. The size is indicated with a suffix to the instruction. The number of elements is indicated by the specified register size and data type of operation. Instructions have the following general format:
V{<mod>}<op>{<shape>}{<cond>}{.<dt>}{<dest>}, src1, src2
Where:
<mod> - modifiers
<op> - the operation (for example, ADD, SUB, MUL).
<shape> - Shape.
Neon data processing instructions are typically available in Normal, Long, Wide and Narrow variants.
<cond> - Condition, used with IT instruction <.dt> - Data type, such as s8, u8, f32 etc. <dest> - Destination <src1> - Source operand 1 <src2> - Source operand 2
Note: {} represents and optional parameter.
For example:
VADD.I8 D0, D1, D2 VMULL.S16 Q2, D8, D9
For more information, please refer to the documents listed in the Appendix.
In the AArch64 execution state, the syntax of Neon instruction has changed. It can be described as follows:
{<prefix>}<op>{<suffix>} Vd.<T>, Vn.<T>, Vm.<T>
<prefix> - prefix, such as using S/U/F/P to represent signed/unsigned/float/bool data type.
<op> – operation, such as ADD, AND etc.
<suffix> - suffix
ADDHN2: add two 128-bit vectors and produce a 64-bit vector result which is stored as high 64-bit part of Neon register.
SADDL2: add two high 64-bit vectors of Neon register and produce a 128-bit vector result.
<T> - data type, 8B/16B/4H/8H/2S/4S/2D. B represents byte (8-bit). H represents half-word (16-bit). S represents word (32-bit). D represents a double-word (64-bit).
UADDLP V0.8H, V0.16B FADD V0.4S, V0.4S, V0.4S
The following table compares the Armv7-A, AArch32 and AArch64 Neon instruction set.
“√” indicates that the AArch32 Neon instruction has the same format as Armv7-A Neon instruction.
“Y” indicates that the AArch64 Neon instruction has the same functionality as Armv7-A Neon instructions, but the format is different. Please check the Armv8-A ISA document.
If you are familiar with the Armv7-A Neon instructions, there is a simple way to map the Neon instructions of Armv7-A and AArch64. It is to check the Neon intrinsics document, so that you can find the AArch64 Neon instruction according to the intrinsics instruction.
New or changed functionality is highlighted.
√
There are four ways of using Neon
The users can call the Neon optimized libraries directly in their program. Currently, you can use the following libraries:
This provides the recommended approach for accelerating AV codecs and supports signal processing and color space conversions.
It is Arm’s open source project. Currently, the Ne10 library provides some math, image processing and FFT function. The FFT implementation is faster than other open source FFT implementations.
Adding vectorizing options in GCC can help C code to generate Neon code. GNU GCC gives you a wide range of options that aim to increase the speed, or reduce the size of the executable files they generate. For each line in your source code there are generally many possible choices of assembly instructions that could be used. The compiler must trade-off a number of resources, such as registers, stack and heap space, code size (number of instructions), compilation time, ease of debug, and number of cycles per instruction in order to produce an optimized image file.
Neon intrinsics provides a C function call interface to Neon operations, and the compiler will automatically generate relevant Neon instructions allowing you to program once and run on either an Armv7-A or Armv8-A platform. If you intend to use the AArch64 specific Neon instructions, you can use the (__aarch64__) macro definition to separate these codes, as in the following example.
Neon intrinsics example:
//add for float array. assumed that count is multiple of 4 #include<arm_neon.h> void add_float_c(float* dst, float* src1, float* src2, int count) { int i; for (i = 0; i < count; i++) dst[i] = src1[i] + src2[i]; } void add_float_neon1(float* dst, float* src1, float* src2, int count) { int i; for (i = 0; i < count; i += 4) { float32x4_t in1, in2, out; in1 = vld1q_f32(src1); src1 += 4; in2 = vld1q_f32(src2); src2 += 4; out = vaddq_f32(in1, in2); vst1q_f32(dst, out); dst += 4; // The following is only an example describing how to use AArch64 specific NEON // instructions. #if defined (__aarch64__) float32_t tmp = vaddvq_f32(in1); #endif } }
Checking disassembly, you can find vld1/vadd/vst1 Neon instruction on Armv7-A platform and ldr/fadd/str Neon instruction on Armv8-A platform.
There are two ways to write Neon assembly:
You can use ".S" or “.s” as the file suffix. The only difference is that C/C ++ preprocessor will process .S files first. C language features such as macro definitions can be used.
When writing Neon assembly in a separate file, you need to pay attention to saving the registers. For both Armv7 and Armv8, the following registers must be saved:
The following is an example of ARM v7-A and ARM v8-A Neon assembly.
For more examples, see GitHub.
You can use Neon inline assembly directly in C/C++ code.
Pros:
Cons:
Example:
// Armv7-A/AArch32 void add_float_neon3(float* dst, float* src1, float* src2, int count) { asm volatile ( "1: \n" "vld1.32 {q0}, [%[src1]]! \n" "vld1.32 {q1}, [%[src2]]! \n" "vadd.f32 q0, q0, q1 \n" "subs %[count], %[count], #4 \n" "vst1.32 {q0}, [%[dst]]! \n" "bgt 1b \n" : [dst] "+r" (dst) : [src1] "r" (src1), [src2] "r" (src2), [count] "r" (count) : "memory", "q0", "q1" ); } // AArch64 void add_float_neon3(float* dst, float* src1, float* src2, int count) { asm volatile ( "1: \n" "ld1 {v0.4s}, [%[src1]], #16 \n" "ld1 {v1.4s}, [%[src2]], #16 \n" "fadd v0.4s, v0.4s, v1.4s \n" "subs %[count], %[count], #4 \n" "st1 {v0.4s}, [%[dst]], #16 \n" "bgt 1b \n" : [dst] "+r" (dst) : [src1] "r" (src1), [src2] "r" (src2), [count] "r" (count) : "memory", "v0", "v1" ); }
Neon intrinsics and assembly are the commonly used Neon. The following table describes the pros and cons of these two approaches:
With the above information, you can choose a Neon implementation and start your Neon programming journey.
This is a simple summary. When applying Neon to more complex scenarios, there will be many special cases. This will be described in my next blog, which you can read by clicking on the link below.
Find out more about how Arm is transforming Edge Computing Arm Neon optimization