Links to a set of technical documents regarding TrustZone for Armv8-M for embedded and IoT security

Cortex-M for beginners

The Arm Cortex-M family now has eight processors. In this paper, we compare the features of various Cortex-M processors and highlight considerations for selecting the correct processor for your application. The paper includes detailed comparisons of the Cortex-M instruction sets and advanced interrupt capabilities, along with system-level features, debug and trace features, and performance comparisons.

Using TrustZone on Armv8-M

This application note explains the features that are available in CMSIS and MDK to utilize the secure and non-secure domains in the Armv8-M architecture. It contains several programming examples, including an RTOS application that shows the interaction of non-secure thread execution with libraries that are provided by the secure domain of an Armv8-M system.

Armv8-M Architecture Technical Overview

A white paper that goes into a technical overview of the Armv8-M architecture and TrustZone for Armv8-M

excerpt: Conceptually TrustZone for Armv8-M is similar to the TrustZone technology found in Arm Cortex-A Processors. The underlying operations of TrustZone for Armv8-M are however very different as they are optimized for embedded systems that require real-time responsiveness, whilst at the same time allowing for high energy efficiency and low silicon area overhead.

The Armv8-M architecture reference manual

This manual documents the microcontroller profile of version 8 of the Arm Architecture, the Armv8-M architecture profile.

TrustZone technology for Armv8‑M Architecture

This document describes the security states, memory partitions, switching between states and calling of secure functions.

System Design for Armv8‑M

This document illustrates a system design with the key extra components and logic that are required to support an Armv8‑M-based microcontroller.

The Next Steps in the Evolution of Embedded Processors for the Smart Connected Era

A technical paper that looks at the capabilities of the next generation of microcontroller products, looking at how they address the needs of system designers and software developers so that they can create the energy efficient, scalable and secure systems that their customers demand.

RTOS design considerations for Armv8‑M based platforms

Describes the changes in Armv8‑M architecture compared to the previous Armv6‑M and Armv7‑M architectures.

Armv8‑M Processor Debug

Debugging is a key part of software development and is often considered to be the most time-consuming part of the process. This document goes through the debug facilities that are provided by Armv8-M.

ACLE Extensions for Armv8‑M 

The Arm C Language Extensions (ACLE) for Armv8‑M describes what updated tools need do to build a secure image and to enable a non-secure image to call a secure image. 

Secure software guidelines for Armv8‑M based platforms

A document that describes new requirements for creating secure software for an Armv8‑M based platform. These include requirements to generate special instructions (BXNS and BLXNS) to branch to Non-secure code and the requirement to preserve and protect Secure register values before calling Secure functions. 

Fault Handling and Detection

A document that describes fault handling and detection in Armv8-M processors.

Armv8‑M Exception Handling

Exceptions are conditions or system events that usually require remedial action or an update of system status by privileged software to ensure smooth functioning of the system. The document describes how the processor responds to an exception, the properties that are associated with each exception, such as its priority level, and the exception return behavior.

Memory Protection Unit for Armv8‑M based platforms

The Memory Protection Unit (MPU) is a programmable unit that allows privileged software to define memory access permissions for up to 16 separate memory regions. This document provides an overview of the MPU programmers' model and summarizes its key features.

Armv8-M processor power management secure state protection

This document describes the interaction between power management in the processor and security implications.

Enhanced Security and Energy Efficiency of Microcontrollers and SoCs 

Abstract— The on-chip system design of microcontrollers and SoCs can have a significant impact on the overall security, power efficiency and responsiveness of the device. This paper outlines the key aspects of the system design and looks at new technology developments that promise to improve the security of these SoCs while still enabling high efficiency and low latency designs.

Introduction to Arm Cortex-M23 and Cortex-M33

A white paper that gives technical details on Cortex-M23 and Cortex-M33

Designing a SoC with Arm Cortex-M (2.0).pdf

Have you ever wondered what it takes to create a small SoC based on a Arm Cortex-M Processor? In this whitepaper, we explain typically what Intellectual Property components are required and what other things you might need to put the whole system together.

AMBA 5 AHB5 Specification

Read the AMBA 5 specification.