Please explain some of the new ACE5 signals in relation to the MASTER and INTERCONNECT behavior

Hi,

The AMBA5 spec for ACE5 shows some new signals versus ACE4 :

VAWQOSACCEPT

VARQOSACCEPT

AWAKEUP

ACWAKEUP

SYSCOREQ

SYSCOACK

How are these used in an SOC system ?

For example, I think but I'm not usre if VAWQOSACCEPT, VARQOSACCEPT is output by each slave and becomes input to INTERCONNECT

or an input to the CPU ?  It's not clear how these signals are related to the other QOS signals in the ACE5 spec.

For AWAKEUP, this is output from a MASTER (CPU ??) to the INTERCONNECT ?  Only used by AXI5, ACE5, ACE5-Lite to wakeup the

interconnect state machine.  Must occur one cycle before ARVALID, AWVALID, WVALID.  It stays high for all transactions.

Becomes low only when the MASTER wants to signal to the INTERCONNECT to go to a semi-low power state.

Wish there were some waveforms to illustrate all the spec description on page 360 (E2.9.1).  It would be much easier to understand.

For ACWAKEUP (ACE5) , this is output from the INTERCONNECT and used by the MASTER (CPU ??) to wake up the logic

in the MASTER (CPU??) from a semi-low power state.  ACWAKEUP must occur at least one cycle high before ACVALID/ACREADY

are active.  Again, wish there were some waveforms to illustrate the spec description on pg 361 (E2.9.2)

For SYSCOREQ (ACE5), this is output from the MASTER (CPU ??)  to connect to a coherency device (INTERCONNECT).

Seems like the MASTER outputs this signal and then the INTERCONNECT device (helping to manage coherency) outputs an acknowledge

to the MASTER for INTERCONNECT to be in correct state machine mode.

Need further explanation with waveforms on four-phase Coherency Connection signaling mentioned on page 362 (E2.10).

When SYSCOREQ goes low what's the behavior of the INTERCONNECT ?

Thanks,

David