From hardware perspective, what's the purpose of WACK and RACK and how does it affect the ACE protocol ?
I can see that the specification says the master issues these two signals to indicate to the interconnect that Write and Read transactions completed
successfully at the master.
What happens on the ACE interface/protocol if NO WACK and RACK occur ?
Please provide some detailed explanations of proper operation of WACK and RACK and improper operation (what if no WACK / RACK occur).
Also, do these two signals (WACK,RACK) occur when WVALID , RVALID , respectively, are still high ?
Are WACK and RACK totally independent of WVALID, RVALID ?
The ACE spec doesn't show any waveform relationship for WVALID, RVALID with respect to WACK and RACK.