Hi. I recently got the ARM AMBA specification in my work, and now I am learning stuffs. But the Additional control information got me stuck for a day haha
My questions are
1. What is the reason to use the Cacheable bit in the Cache support? I wish I could get the example In real industry standard.
2. When reading the speicfication on the Cacheable bit, they say the multiple write can merge together in multiple writes. I cannot catch the viivd picture on this situation. Does this mean the several master can write the data on cache? can i get some real life example so that I can visualize the real problem with this write section?
3. I want to check whether I understand right in read section. So if the read happens with the cacheable bit flag HIGH, it means the data which the Master wants to read from the memory could be cached in the cache nearby the Master. And the principle of the Cache getting the data nearby the address which the Master asks to the Slave get applied here so some are 'pre-fetched' in the Cache. Is this right to understand what the specification explains??
What I feel while writing this question is that all understanding I have right now is all wrong. I feel like I got a wrong start move from the beginning.
Hi Paramo.
Could you please clarify two terms specified in the spec: "Memory type" and "Transaction attributes" both of them refer to AxCHACHE signals.
If I'm correctly understand the "Memory type" specifies characteristic of memory attached to the slave port. It can be Normal or Device, Cacheable, etc.
What I do not understand how master port can handle the behavior of memory through AxCHACHE signals? For example what happens if Master issues Write-back Read and Write-allocate transaction to the memory which physically doesn't have caches?
Or each Master must know the type of memory in the Slave and send only correct transactions?
Thank you in advance and sorry if my question is silly. :)
AlexR said:
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Your understanding of memory types is correct. The transaction attributes include the memory type and all the other information encoded on the Ax channels.
Fundamentally, yes the master does need to know the nature of the slave that it's targeting. If it's performing a register access, then the memory type should be Device.
It also needs to be ensured that all the masters in the system are accessing the same region with the same memory attributes, as otherwise memory consistency could be lost. For example, a Device access to region would not access any caches, and so might not see a cacheable write to the same region.
As it happens, the example you give wouldn't be a problem. If a master issued an allocatable cacheable access to a region that didn't have a cache, then the allocation hints would just be ignored and the access would be made to and from main memory.