The ETB/ETF sitting in the trace path may be used as a circular buffer (capture) trace sink or configured into hardware FIFO mode or software FIFo mode. So how to choose which mode need to br programme for which trace ??
It depends on what type of environment and component you are working with. The "Operational modes" section of the CoreSight Trace Memory Controller Technical Reference Manual at infocenter.arm.com/.../CACHCCID.htmlsays:"Hardware FIFO mode This mode is available only in the ETF configuration. The component uses its storage as a FIFO and acts as a link between a trace source, and a trace sink. No trace is lost or overwritten, and back pressure is applied through ATB to the trace source when the FIFO becomes full. Most trace sources eventually overflow when subject to back-pressure for a long time, but it is always the trace sources that lose trace, not the ETF. This mode enables peaks in trace bandwidth requirement to be smoothed, and reduces the requirement to exert back-pressure, so that: trace can be output over a trace port using fewer pins than would be required without the ETF, by smoothing peaks in trace bandwidth over long periods trace that is output over a subsequent ETR can cope with memory system latency caused by higher priority masters on the interconnect, without the loss of trace. Software FIFO mode This mode is available in all configurations. In this mode, the component functions as a FIFO, where data is read out over an APB interface, usually by an external debugger. This provides a low-speed off-chip communication channel for retrieving trace data, reusing the existing JTAG or Serial Wire Debug (SWD) connection."I hope this helps.