MBERROR : AHB Master bus error status, set when the AHB Master encounters a bus error response from a slave

Hi,

Facing the issue:
"MBERROR :  AHB Master bus error status, set when the AHB Master encounters a bus error response from a slave"

Here is the Inputs:

We are using the custom SOC, in which we are testing the CLCD controller(IP ARM PL111)
connected the TFT LCD 24 Bit mode on the Board , Configured the PL111 Registers based on the LCD.
(Base address of CLCD : 0xD4554000) (LCD Resolution: 800X480)

Dump of the Registers:
Address: d4554000        Value of tim0 REG: 0x2ed228c4
Address: d4554004        Value of tim1 REG: 0x171851df
Address: d4554008        Value of tim2 REG: 0x31f000a
Address: d455400c        Value of tim3 REG: 0x10000
Address: d4554010        Value of ubas REG: 0x3fed6000
Address: d4554014        Value of lbas REG: 0x0
Address: d4554018        Value of cntl REG: 0x1092b
Address: d4554020        Value of stat REG: 0x14
Address: d4554024        Value of intr REG: 0x0
Address: d4554028        Value of ucur REG: 0x0
Address: d455402c        Value of lcur REG: 0x3fed6000
Address: d4554200        Value of palette REG: 0x4a93b220
Address: d4554800        Value of crsrimg REG: 0x20518640
Address: d4554c00        Value of crsrctrl REG: 0x0
Address: d4554c04        Value of crsrcnfg REG: 0x0
Address: d4554c08        Value of crsrplte0 REG: 0x0
Address: d4554c0c        Value of crsrplte1 REG: 0x0
Address: d4554c14        Value of crsrclip REG: 0x0


Raw Interrupt Status Register Value:  0x14

Name     Baseoffset     Type     Reset value     Description
LCDRIS     0x020         RO     0x0         Raw Interrupt Status Register

In "LCDRIS" Register, MBERROR(bit 5) is set

Technical Reference Manual of PL111 Says:
MBERROR :  AHB Master bus error status, set when the AHB Master encounters a bus error response from a slave.

Please help out to resolve the issue.

Regards,
Ratan