I am a Digital Verification Design Engineer.
Currently, I am in the process of developing an UVM Test Bench for AHB 2.0.
I have following questions.
1) From AHB Master side, Can BUSY cycles be inserted in middle of INCR16 burst?
2) From AHB Master side, Can BUSY cycles be inserted in middle of WRAP16 burst?
Hi jd,
I have a question concerning insertion of busy cycles in a defined length burst.
When a master inserts a busy transfer, should the HREADY signal from the slave be LOW till the master inserts a SEQ transfer ?
Regards,
Hi momran,
No, HREADY should be driven as required for the current data phase transfer.
So if the slave is currently performing the data phase operation of a SEQ access while the master is signalling a BUSY transfer address phase, the slave should just signal whatever wait states it needs for the SEQ transfer, and only once that SEQ transfer data phase has completed does the slave then move onto the data phase of the next transfer (the BUSY in this example).
For the data phase of a BUSY transfer the slave must respond with HREADY high and HRESP=OKAY.
As an example, have a look at figure 3-6 in the AHB spec. It shows a BUSY cycle following a NONSEQ in an undefined length burst. The slave isn't adding wait states to any of the transfers in this sequence.
JD