Dear ARM Support Team,
I am currently integrating the Cortex-M0 CPU and writing SDC constraints for STA analysis. I observed several reg-to-reg timing violations inside the Cortex-M0 design and would like to ask: * Are these violations expected in some cases? * Is it allowed/recommended to use `set_multicycle_path` or `set_false_path` for such violated paths? * If yes, could you please explain the functional or architectural reason? * Could you also share any recommended SDC guidelines or a reference SDC example for Cortex-M0? I would like to avoid adding timing exceptions without understanding the intended timing behavior. I have attached the timing.log report and the constraint file used for this analysis for your reference.
Thank you for your support. Best regards,
https://drive.google.com/drive/folders/1r7gOi4jrRGQ2UBSJnB4lzM1HPEoUtkhc?usp=sharing