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Hi,
My understanding is that, whenever master samples HREADY HIGH, it knows that the slave has sampled the current address and control signals, so master starts the address phase for the next transaction (Statement1). I am proceeding assuming my understanding is correct, please correct me if I am wrong here.
Let's say we have one AHB mater and 2 AHB slaves - M0, S1, S2. M0 initiates few transactions to S1 first, then starts issuing transactions to S2.
When the master samples the HREADY as HIGH from S1's penultimate data phase, it also means that S1 has sampled the current address and control signals, which is the final address phase for S1, and hence it starts the S2's 1st transactions address phase (from Statement1). Now, from S2 point of view, HREADYIN signal indicates when the data phase of last transaction of S1 is finished. When this HREADYIN for the last transaction of S1 is asserted, S2 sees HSEL asserted and knows that this transaction is intended for S2. But if S2 is driving HREADY LOW at this point (all the while till this point), will the master sample the HREADY of S1 and start S2's 2nd transaction's address phase? If that is the case, now whenever S2 drives HREADY HIGH, will the master think that the S2's 1st transaction's data phase is finished and start S2's 3rd transaction address phase? Because S2 hasn't provided the 1st transaction's data/resp yet, disrupting the pipeline nature of AHB
Assuming S2 drives HREADY LOW from the very beginning till few cycles after S1's final data phase,
1. At what point does M0 change the address phase from S1's last transaction to S2's first transaction?
2. At what point does S2 start its first transaction's data phase?
3. At what point does S2 sample the first transaction's address and control signals?