"I want to create simple tasks to send address and data from the master to the slave without any burst-length violations, making sure to include wstrb.
wstrb
When an AXI4 master and AXI3 slave are connected via an NoC bus and perform transactions, the AXI4 master is set with awburst = 1, awlen = 1, awsize = 2, and wdata is 64-bit. Meanwhile, the AXI3 slave is configured to receive inputs with awburst = 1, awlen = 1, awsize = 2, and wdata is fixed at 32-bit.
awburst = 1
awlen = 1
awsize = 2
wdata
I think that if the master sends a 64-bit transfer in one burst, and the slave receives it as two 32-bit transfers, there shouldn’t be any protocol issues. However, GPT suggests that the awlen of the AXI4 master and AXI3 slave must match to avoid burst-length violations. If I make awlen match, it will change the original behavior I intended.
awlen
In what cases does a burst-length violation occur?"
Apologies for the confusion. The first issue regarding the 2-byte transaction has been resolved by using 64-bit data. Initially, I thought that if I sent two 32-bit transactions, I should only provide 32-bit data. So I mistakenly wrote something like this: wdata[63:0] = my_data[31:0] and then wdata[63:0] = my_data[63:32]. This was my mistake—I should have used 64-bit data directly for wdata[63:0]. So this issue has been cleared up.
wdata[63:0] = my_data[31:0]
wdata[63:0] = my_data[63:32]
wdata[63:0]
My last question was about using a 4-byte increment for addressing, but I encountered bus hangs and incorrect results when the addresses were not multiples of 8. After investigating, I realized that the bus only works correctly when the addresses are multiples of 8. I’m now wondering what determines this alignment requirement for bus addressing. and your answer makes me clear. Thanks.