For PWAKEUP signal, it is specified that "If a completer clock is gated independently of the requester clock and PWAKEUP is used to enable the completer clock, there is a possibility that the setup phase of a transfer is missed by the completer"

Ravi Kothiya said:

Like they have specified the scenario but there is not any kind of further information in specification like whether we have to accept such transfers as valid or not? 

Yes, these transfers are valid.  If the downstream component can be clock-gated independently of the upstream component, then the upstream component does not know if the downstream component is clock gated or when it will be un-clock-gated and so will assume that any APB transfer it sends will receive the expected response.

Hence, the specification states that it recommends that both interfaces are clock-gated together.

It's also possible that the subordinate interface can be designed such that even if it misses the setup phase, then it can still respond appropriately.  When clock-gated, the subordinate can hold PREADY low to extend the access phase.  When it exits the clock-gated state, it could support entering directly into the access phase and still respond appropriately and assert PREADY when appropriate.

Ravi Kothiya said:

Also Why there is no mention of PWAKEUP signal in FSM State even if it is an important signal for APB5 perspective.

PWAKEUP can be considered orthogonal to the basic APB operation and would not have any impact on how this state machine transitions.

Ravi Kothiya said:

Like they have specified the scenario but there is not any kind of further information in specification like whether we have to accept such transfers as valid or not? 

Yes, these transfers are valid.  If the downstream component can be clock-gated independently of the upstream component, then the upstream component does not know if the downstream component is clock gated or when it will be un-clock-gated and so will assume that any APB transfer it sends will receive the expected response.

Hence, the specification states that it recommends that both interfaces are clock-gated together.

It's also possible that the subordinate interface can be designed such that even if it misses the setup phase, then it can still respond appropriately.  When clock-gated, the subordinate can hold PREADY low to extend the access phase.  When it exits the clock-gated state, it could support entering directly into the access phase and still respond appropriately and assert PREADY when appropriate.

Ravi Kothiya said:

Also Why there is no mention of PWAKEUP signal in FSM State even if it is an important signal for APB5 perspective.

PWAKEUP can be considered orthogonal to the basic APB operation and would not have any impact on how this state machine transitions.