Hi There,
I have small doubts in wrap calculation
for suppose I have start address 0x04 and HSIZE = 0(one byte) and HBURST = 2(4 beat wrapping burst)
for suppose I have start address 0x38 and HSIZE = 1(two byte) and HBURST = 2(4 beat wrapping burst)
can any one help me to calculate the wrap for above number with detailed calculations
WRAP bursts transfer data within an HSIZE and burst length aligned range.
So taking your first example, with HSIZE=byte and length 4, we are looking at a 4 byte aligned range. As the start address of the burst (0x04) is already 4 byte aligned, there will be no wrap point, so the burst will simply access 0x04, 0x05, 0x06 and 0x07.
Similarly with your second example, HSIZE is 2 bytes and length is 4, so an 8 byte aligned range. With the start address 0x38 being 8 byte aligned we again don't have any wrapping, so the burst will be to 0x38, 0x3A, 0x3C and 0x3E.
If this second burst had started at 0x3A, then you would have had transfers after this to 0x3C, 0x3E and wrapping back to 0x38 to finish the burst.
I'm not sure what detailed calculations you are looking for, but the above is how I work it out.
Hi Colin,
Thank you for you answer
I have one doubt what is four or eight byte alligned how can we say one address is 4 byte alligned and 8 byte aligned like that.
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Wrap_Boundary = (INT(Start_Address/(Number_Bytes×Burst_Length)))×(Number_Bytes×Burst_Length)
Address_N = Wrap_Boundary + (Number_Bytes × Burst_Length)
I am using the above two formulas to calculate wrap boundary and address at which it need to wrap.
when I am using number like having zeros in 1, 2, 4, 8 positions (for example, number like 4, 8, 16, 32it is not wrap it is incrementing), i think the calculation is wrong.
An address is 4 byte aligned if it can be divided by 4, so any address ending 0x0, 0x4, 0x8 or 0xC. Similarly 8 byte aligned if it can be divided by 8, so ending 0x0 or 0x8.
But if we are looking at typical uses of wrapping bursts, they are using in cache related accesses, where a critical data entity is accessed first, and then a longer cache line if filled up around the critical entity. Here we would usually be looking at an HSIZE value of at least word (4 byte), and cache line lengths of at least 4, and more likely 8 or 16, so the wrapping boundary for a 4-word cache line is 16 byte aligned, so addresses divisible by 16 (ending 0x0).
I've never liked those calculations you have quoted from the AXI spec as I think they are more complex than just simply understanding what a wrapping burst is and where it should wrap.
But if we try to use them, the "Wrap_Boundary" calculation gives you the address the wrapping burst will wrap back to. It doesn't tell you the address at which you would then wrap back. So that is why the text in the spec says if Address_N =Wrap_Boundary + (Number_Bytes X Burst_Length), which does tell you the incremented address that you would instead have wrapped back to Wrap_Boundary.
At that point you use "Wrap_Boundary" as this transfer address, and then subsequent addresses use the Address_N = Start Address + ((N-1) x Number_Bytes) - (Number_Bytes x Burst_Length).
Where you are using a WRAP burst that starts from a burst aligned address, there isn't any wrapping, so the "if Address_N = Wrap_Boundary + (Number_Bytes x Burst_Length)" test is never true, so all the equations still work.
For example if we take your very first example, start address HADDR=0x4, HSIZE=0x0 (byte) and HBURST=0x2 (WRAP4), we have Number_Bytes =1 and Burst_Length=4, so...
Wrap_Boundary = (INT(0x4 / (1 * 4))) x (1 x 4) = 4.
The "if Address_N = Wrap_Boundary + (Number_Bytes x Burst_Length)" test then tests for the address reaching 0x4 + (1 x 4), so 0x8. This address will never be reached because we know the incrementing address will be 0x4, 0x5, 0x6 and finally 0x7 after the 4th transfer. Burst has ended, so wrapping point never reached.
The calculations do work in all cases if you read the full text in this section of the AXI spec.