I have an AXI4 initiator that issues a 32-bit read request to an AXI target (memory) via a 64-bit wide data bus.
I set the ARSIZE parameter to 2.
The data in the target memory are the following:addr : data0x000: 64'h 77_66_55_44_33_22_11_000x100: 64'h 00_00_00_00_00_00_00_00
I am getting the following response data at the initiator interface:
In all cases, burst_type = INCR and burst_len = 0
case1: raddress = 'd0; ARSIZE= 'd2;rdata_rcvd: 64'h 77_66_55_44_33_22_11_00 rdata_expected = 64'h 77_66_55_44_33_22_11_00
case2: raddress = 'd4; ARSIZE= 'd2rdata_rcvd: 64'h 77_66_55_44_33_22_11_00 rdata_expected = 64'h xx_xx_xx_xx_77_66_55_44
case3: raddress = 'd5; ARSIZE= 'd2
rdata_rcvd: 64'h 77_66_55_44_33_22_11_00 rdata_expected = 64'h xx_xx_xx_xx_77_66_55_44
In case2 and case3, I expected that the slave aligns the 32-bit data on bits 0 to 32 of the 64-bit data bus.Does the slave behaves correct or my understanding of ARSIZE parameter is wrong?
Your solution is one possible alternative solution, but something has to change the position of the data from the byte lanes corresponding to the address to the LSBs of the data bus. It is the initiator that requests the data, so it should be the one to do any data manipulation once received. The target should just provide the data bytes requested, and using the byte lanes corresponding to the address for the transfer.
There may be some obscure applications where the initiator WANTS the bytes to remain in the MSBs (or the correct byte lanes), perhaps it is performing a read/modify/write sequence, so it doesn't want the target to "manipulate" the data before returning it.
So best leave the initiator to do any data manipulation required as it is the module that knows what it wants to do with the data.
Ok. Thank you for the answer