I'm running a simple bare-metal application on Armv8-R AEM FVP (FVP_BaseR_AEMv8R 11.20.15). For the same exact code on the model's Armv8-A counterpart (FVP_Base_RevC-2xAEMvA), I noticed that setting cache_state_modelled=0 considerably speeds up emulation. However, when I apply the same option o FVP_BaseR_AEMv8R, the model does not seem to work. I would suspect the app's code if it was the other way around (i.e., stop working when enabling cache modeling), but couldn't see how disabling it would impact it. A bit of debugging lead me to conclude that the exclusive ld/st instructions stopped working. Section "2.4.7 Global exclusive monitor in Fast Models" in Fast Models Reference Guide 11.20, seems to imply that when cache_state_modelled=0, there is some backup implementation for the exclusive monitor that does not rely on the coherence protocol thus not depending on cache state modelling. This seems to be true for FVP_Base_RevC-2xAEMvA but not for FVP_BaseR_AEMv8R 11.20.15. Any idea on might be going wrong?
Thank you for creating a support ticket. We will follow up on this through the support case.