Hi, I just wondering if there is a bridge<AXI data(64bit) to AHB data(32bit)>.
I know there is an IP(AHB LITE to AXI) in Xilinx. But it just support ONLY the 64bit to 64bit or 32bit to 32bit.
Thank you..
The NIC-400 is designed to be a multi-source, multi-destination configurable AXI interconnect.
But in its simplest form it is a single source to single destination component, not then requiring any address decoding and routing logic, and so is a configurable bridge.
So the bridge isn't included in the NIC-400 network, it IS the NIC-400 interconnect (in its simplest form).
You can also specify an AXI interconnect, with external interfaces that can be AXI3, AXI4, AHB-lite or APB protocol, and these "bridge" functions will then be implemented before or after the central AXI structure as part of the NIC-400 interconnect to give the required external interface protocols, data widths and clock domains.
Hi, First of all thank you for your guidance.
But I am confused whether the Bridge is included in NIC-400 Network or not.
Actually I heard the NIC-400 Network first time in forever.
Anyway thank you for your help.
Best regards,
Are you asking about Xilinx IP (in which case you should probably ask on a Xilinx forum), or are you asking about Arm IP ?
If Arm IP, yes, you can use Arm's NIC-400 AXI interconnect product to generate a large number of bridge configurations, supporting any combinations of clock domain crossings, data width conversions, and protocol conversions.
So generating an AXI (AXI3 or AXI4) to AMBA 3 AHB-lite bridge that also downsizes from 64-bits to 32-bits with NIC-400 is definitely supported.